cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Observer
Observer
501 Views
Registered: ‎04-25-2018

Interlaken Crossbar

Jump to solution

Hello,

I am trying to connect our control code for the 40G/50G v1.0 ethernet subsystem that uses the Straddled AXI4-Stream (really it's 128 bit Interlaken with 2 64 bit segments where SOP/EOP/MTY/ERR are on the tuser lines) to the 100G CMAC ethernet subsystem (which can use 512 bit AXI4-Stream or 512 bit Interlaken LBUS with 4 128 bit segments). The part I'm struggling with is converting from the 128 bit 2 segment LBUS to 512 bit 4 segment LBUS for the 100G core. Is there an Interlaken crossbar that can take care of doing this? The interface is not complicated, but the difficult part is keeping track of SOP/EOP/ERR/MTY when changing segment widths from 64 bits to 128 bits. The part I am struggling to figure out is keeping track of is when eop0=sop1=1 which causes mis-alignment in the 128 bit LBUS 100G segment since I would now have to mis-align the incoming TX LBUS transaction such that I could only fill the following 100G segment with 64 bits associated with the SOP and wait for the next transaction to fill the remainder of that segment. Until the next EOP/SOP pair, my transactions will be mis-aligned. For Ethernet RX I don't really care as I can just avoid overlapping, but the TX direction is just super annoying to deal with in HDL.

 

My current idea is to convert the 40G/50G TX/RX datapath to 128 bit AXI4-Stream, then change widths to 512 bit AXI4-Stream. Then I would just set the 100G CMAC to use AXI4-Stream instead of LBUS. Then, we can drive the 100G CMAC with our old 40G control code. When I select AXI4-Stream in the CMAC, the *_lbus2axis_segmented_top.v is created which is nice, but the same is not created when I select the 256 bit AXI4-Stream in the 40G/50G ethernet subsystem v3.0.

 

Below are the waveforms for the 100G CMAC and the 40G/50G EMAC respectively:

glennicholls_0-1603232793144.pngglennicholls_1-1603232824976.png

 

0 Kudos
Reply
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
434 Views
Registered: ‎04-16-2008

There is not anything planned at this time.

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

3 Replies
Xilinx Employee
Xilinx Employee
445 Views
Registered: ‎04-16-2008

For 100G CMAC, the LBUS interface is port interface to the hard block so AXIS to LBUS conversion logic is provided as a wrapper file.  Since the 40G Ethernet core is a soft core there isn't a similar 256-bit AXIS non-segmented to 128-bit AXIS segmented conversion file and the different interface as just built into the core, but the core does have option to generate with 256-bit AXIS non-segmented interface in latest version of the IP.  

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Reply
Observer
Observer
438 Views
Registered: ‎04-25-2018

Got it, are there plans to implement an Interlaken crossbar IP? I've looked around the forums on similar topics and it looks like that kind of IP would be useful in similar cases to mine. Notably, cases where BW is critical and AXIS is avoided in favor of LBUS but width changing is needed to interface two LBUS peripherals with different requirements.

0 Kudos
Reply
Xilinx Employee
Xilinx Employee
435 Views
Registered: ‎04-16-2008

There is not anything planned at this time.

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post