01-31-2017 11:39 AM
02-08-2017 02:13 AM
Hi
The whole core comes as an single encrypted file and there are no separate individual block files available for users.
01-31-2017 06:45 PM
@bcarltontrex it's possible that this is done at a higher speed clock portion of the hardwired design and it is most probably not available back to the fabric.
02-01-2017 08:56 AM
02-06-2017 06:27 AM
Hi
The scrambler and decoder/encoder are part of the encrypted core logic and only the XGMII interface is present at the top level,how ever you can add the block output in the ILA from the synthesized netlist if it is only for testing purpose.
02-07-2017 02:48 PM
The documentation confirms most of it is in logic
10GBASE-R
For Zynq®-7000, UltraScale™, Virtex®-7, and Kintex®-7 devices, all of the PCS and
management blocks illustrated are implemented in logic, except for part of the Gearbox and
SERDES. Figure 1-1 shows the architecture.
02-07-2017 02:49 PM
@yenigal, are the sub-block available? Even if encrypted that would be helpful for my application.
02-08-2017 02:13 AM
Hi
The whole core comes as an single encrypted file and there are no separate individual block files available for users.
02-08-2017 07:46 PM
@bcarltontrex one thing you can do is to implement the block and look at the hierarchy. If you can figure out what the decoder looks like you can just include the whole encrypted netlist and use the portions you need.