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bcarltontrex
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Registered: ‎01-30-2017

Is the receive data prior to 64b/66b decoder available from 10 Gig Eth PCS?

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I'm looking for the 66-bit data that is after the scrambler, but before it is put into XGMII format. I'm using Virtex-7, Vivado 2016.4.

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yenigal
Xilinx Employee
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Registered: ‎02-06-2013

Hi

 

The whole core comes as an single encrypted file and there are no separate individual block files available for users.

Regards,

Satish

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muzaffer
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Registered: ‎03-31-2012

@bcarltontrex it's possible that this is done at a higher speed clock portion of the hardwired design and it is most probably not available back to the fabric.

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bcarltontrex
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@muzaffer, I don't think that's the reason. While the SERDES logic is fast, the parallel input/output is at 156.25 MHz only.

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yenigal
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Hi

 

The scrambler and decoder/encoder are part of the encrypted core logic and only the XGMII interface is present at the top level,how ever you can add the block output in the ILA from the synthesized netlist  if it is only for testing purpose.

 

 

Regards,

Satish

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bcarltontrex
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The documentation confirms most of it is in logic

 

10GBASE-R
For Zynq®-7000, UltraScale™, Virtex®-7, and Kintex®-7 devices, all of the PCS and
management blocks illustrated are implemented in logic, except for part of the Gearbox and
SERDES. Figure 1-1 shows the architecture.

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bcarltontrex
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@yenigal, are the sub-block available? Even if encrypted that would be helpful for my application.

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yenigal
Xilinx Employee
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Registered: ‎02-06-2013

Hi

 

The whole core comes as an single encrypted file and there are no separate individual block files available for users.

Regards,

Satish

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muzaffer
Teacher
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Registered: ‎03-31-2012

@bcarltontrex one thing you can do is to implement the block and look at the hierarchy. If you can figure out what the decoder looks like you can just include the whole encrypted netlist and use the portions you need. 

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