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Contributor
Contributor
500 Views
Registered: ‎04-12-2018

JESD RX sync not asserted

Hi,

 

I have interfaced KC705 with TI ADC ADS42JB49 . The JESD RX configuration on FPGA is LMF_222, 3.125Gbps, K=32, ref_clk = 156.25MHz and glbl_clk = 78.125MHz.

 

I observe that sysref pulses are captured at FPGA side but sync~ is always low. The sync status reg reads value 00010000 (sysref captured and link sync not acheived ).

 

What can I test on FPGA side to debug this further.

 

jesd_rx_sync.PNG

 

Thanks,

Yogitha 

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1 Reply
Observer yawenluo16
Observer
248 Views
Registered: ‎05-28-2019

Re: JESD RX sync not asserted

Hi Yogitha,

Greetings here! Did you figure it out? I'm facing the same problem as you, I think I've given the same/right link configurations to both JESD Rx and Tx, but just could not see the SYNC asserted at Rx even after SYSREF pulse is detected. 

Please kindly let me know how you get it worked, any info will be appreciated. I get stuck and really don't know where to debug. Thanks!

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