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Observer tyhero
Observer
850 Views
Registered: ‎06-15-2018

JESD sync is wrong

Hi,

 

I am using KCU105 to interface with 14bit ADC by JESD204B. Currently, I found the phy core (jesd204_phy_0) output data is wrong. It should have be "bcbcbcbc" to build the sync. I attached the waveform files for this. I set the xdc file as below. Could you please tell me how to deal with it?

 

##############################################################################
# CLOCK CONSTRAINTS
###############################################################################

# Set Reference Clock
# 515.625MHz
create_clock -period 1.939 -name refclk [get_ports adc_jesd204_clkp]

# Set Device Clock - JESD204 core_clk applied at both the clock input pin and bufgmux output.
# 257.813MHz
create_clock -period 3.878 -name glbclk [get_ports adc_jesd204_glblclkp]
create_clock -period 3.878 -name coreclk [get_pins jesd204_0_ex_u/i_jesd204_0_support_block/i_shared_clocks/glbl_bufg_i/O]

# Set DRP Clock to 100.0MHz
create_clock -period 10.000 -name jesd204_0_drpclk [get_ports adc_drpclk]

# Set AXI-Lite Clock to 100.0MHz by default
#create_clock -period 10.000 -name jesd204_0_axi_aclk [get_ports s_axi_aclk]
###############################################################################
# IO constraints
###############################################################################

set_property PACKAGE_PIN {} [get_ports adc_jesd204_glblclkp]
set_property PACKAGE_PIN {} [get_ports adc_jesd204_glblclkm]
set_property PACKAGE_PIN {} [get_ports adc_jesd204_clkp]
set_property PACKAGE_PIN {} [get_ports adc_jesd204_clkm]
###########
set_property PACKAGE_PIN AD10 [get_ports adc_sysreset]
set_property IOSTANDARD LVCMOS18 [get_ports adc_sysreset]
##
set_property PACKAGE_PIN H11 [get_ports adc_jesd204_glblclkp]
set_property PACKAGE_PIN G11 [get_ports adc_jesd204_glblclkm]
set_property IOSTANDARD LVDS [get_ports adc_jesd204_glblclkp]
set_property IOSTANDARD LVDS [get_ports adc_jesd204_glblclkm]
#
set_property PACKAGE_PIN K6 [get_ports adc_jesd204_clkp]
set_property PACKAGE_PIN K5 [get_ports adc_jesd204_clkm]


set_property PACKAGE_PIN K20 [get_ports adc_drpclk]


set_property PACKAGE_PIN A13 [get_ports adc_rx_sysref]

set_property PACKAGE_PIN G10 [get_ports ila_clk]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets adc_drpclk_IBUF_inst/O]

#set_property PACKAGE_PIN F10 [get_ports adc_axi_aclk]
#set_property IOSTANDARD LVDS [get_ports adc_jesd204_clkp]
#set_property IOSTANDARD LVDS [get_ports adc_jesd204_clkm]
#set_property PACKAGE_PIN A13 [get_ports adc_jesd204_sysrefp]
#set_property PACKAGE_PIN A12 [get_ports adc_jesd204_sysrefm]
set_property PACKAGE_PIN B15 [get_ports adc_sync]
#set_property IOSTANDARD LVDS [get_ports adc_sync]

set_property PACKAGE_PIN E4 [get_ports adc_jesd204_dap]
set_property PACKAGE_PIN E3 [get_ports adc_jesd204_dam]


set_property PACKAGE_PIN D2 [get_ports adc_jesd204_dbp]
set_property PACKAGE_PIN D1 [get_ports adc_jesd204_dbm]
set_property PACKAGE_PIN B2 [get_ports adc_jesd204_dcp]
set_property PACKAGE_PIN B1 [get_ports adc_jesd204_dcm]
set_property PACKAGE_PIN A4 [get_ports adc_jesd204_ddp]
set_property PACKAGE_PIN A3 [get_ports adc_jesd204_ddm]

 

 

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3 Replies
Xilinx Employee
Xilinx Employee
778 Views
Registered: ‎10-19-2011

Re: JESD sync is wrong

Hi @tyhero,

 

please look also at the data status bits that tell you if there is a K character seen or disparity and notintable errors (RXCTRL).

Also check the transceiver startup. Is it finished? In which state is the startup FSM? Did alignment happen already?

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Observer tyhero
Observer
761 Views
Registered: ‎06-15-2018

Re: JESD sync is wrong

Hi,

 

Thank you.

 

I did not find the data status bits. or I did not know how to check the transceiver startup. I read the pg198 and still comfuse how to debug JESD. Please tell me more.

 

I also posted the below code. Can you tell me which signals I will check?

 

jesd204_0 jesd204_i
(

// Rx
.rx_reset (rx_reset),
.rx_core_clk (rx_core_clk),

.rx_sysref (rx_sysref),
.rx_sync (rx_sync),

// Ports Required for GT
.rx_reset_gt (rx_reset_gt),

.rxencommaalign_out (rxencommaalign_i),
.rx_reset_done (rx_reset_done),

// Lane 0
.gt0_rxdata (gt0_rxdata),
.gt0_rxcharisk (gt0_rxcharisk),
.gt0_rxdisperr (gt0_rxdisperr),
.gt0_rxnotintable (gt0_rxnotintable),

// Lane 1
.gt1_rxdata (gt1_rxdata),
.gt1_rxcharisk (gt1_rxcharisk),
.gt1_rxdisperr (gt1_rxdisperr),
.gt1_rxnotintable (gt1_rxnotintable),

// Lane 2
.gt2_rxdata (gt2_rxdata),
.gt2_rxcharisk (gt2_rxcharisk),
.gt2_rxdisperr (gt2_rxdisperr),
.gt2_rxnotintable (gt2_rxnotintable),

// Lane 3
.gt3_rxdata (gt3_rxdata),
.gt3_rxcharisk (gt3_rxcharisk),
.gt3_rxdisperr (gt3_rxdisperr),
.gt3_rxnotintable (gt3_rxnotintable),

// Rx AXI-S interface for each lane
.rx_aresetn (rx_aresetn),

.rx_start_of_frame (rx_start_of_frame),
.rx_end_of_frame (rx_end_of_frame),
.rx_start_of_multiframe (rx_start_of_multiframe),
.rx_end_of_multiframe (rx_end_of_multiframe),
.rx_frame_error (rx_frame_error),

.rx_tdata (rx_tdata),
.rx_tvalid (rx_tvalid),

// AXI-Lite Control/Status
.s_axi_aclk (s_axi_aclk),
.s_axi_aresetn (s_axi_aresetn),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
.s_axi_bresp (s_axi_bresp),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bready (s_axi_bready),
.s_axi_araddr (s_axi_araddr),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
.s_axi_rdata (s_axi_rdata),
.s_axi_rresp (s_axi_rresp),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready)
);

 

jesd204_phy_0
i_jesd204_phy (
// Reset Done for each GT Channel
.gt_txresetdone (),
.gt_rxresetdone (),

// CPLL Lock for each GT Channel
.gt_cplllock (),

// Loopback
.gt_loopback (12'b0),

.gt_txprbsforceerr (4'b0),

.gt_rxprbssel (16'b0),
.gt_rxprbscntreset (4'b0),
.gt_rxprbserr (),

// Transmit Control
.gt_txpostcursor ({4{5'b00000}}),
.gt_txprecursor ({4{5'b00000}}),

.gt_txdiffctrl ({4{4'b1100}}),
.gt_txpolarity (4'b0),
.gt_txinhibit (4'b0),

.gt_rxpolarity (4'b0),

// Power Down Ports
.gt_rxpd ({4{2'b00}}),
.gt_txpd ({4{2'b00}}),

// TX Reset and Initialization
.gt_txpcsreset (4'b0),
.gt_txpmareset (4'b0),

// RX Reset and Initialization
.gt_rxpcsreset (4'b0),
.gt_rxpmareset (4'b0),
.gt_rxbufreset (4'b0),
.gt_rxpmaresetdone (),

// TX Buffer Ports
.gt_txbufstatus (),

// RX Buffer Ports
.gt_rxbufstatus (),

// PCI Express Ports
.gt_rxrate (12'b0),

// RX Margin Analysis Ports
.gt_eyescantrigger (4'b0),
.gt_eyescanreset (4'b0),
.gt_eyescandataerror (),

// RX Equalizer Ports
.gt_rxdfelpmreset (4'b0),
.gt_rxlpmen ({4{1'b1}}),

// RX CDR Ports
.gt_rxcdrhold (4'b0),

// RX Digital Monitor Ports
.gt_dmonitorclk (4'b0),
.gt_dmonitorout (),

// RX Byte and Word Alignment Ports
.gt_rxcommadet (),

.gt_pcsrsvdin (64'b0),

// Reset Inputs for each direction
.tx_reset_gt (rx_reset_gt),
.rx_reset_gt (rx_reset_gt),
.tx_sys_reset (rx_reset),
.rx_sys_reset (rx_reset),

.cpll_refclk (refclk),

// Reset Done for each direction
.tx_reset_done (),
.rx_reset_done (rx_reset_done),

.gt_powergood (),

.rxencommaalign (rxencommaalign_i),

// Clocks
.tx_core_clk (rx_core_clk),
.txoutclk (),

.rx_core_clk (rx_core_clk),
.rxoutclk (),

.drpclk (drpclk),

//Tx PRBSSEL Pattern Generator
.gt_prbssel (4'b0),

// DRP Ports

.gt0_drpaddr (9'd0),

.gt0_drpdi (16'd0),
.gt0_drpen (1'b0),
.gt0_drpwe (1'b0),
.gt0_drpdo (),
.gt0_drprdy (),


.gt1_drpaddr (9'd0),

.gt1_drpdi (16'd0),
.gt1_drpen (1'b0),
.gt1_drpwe (1'b0),
.gt1_drpdo (),
.gt1_drprdy (),


.gt2_drpaddr (9'd0),

.gt2_drpdi (16'd0),
.gt2_drpen (1'b0),
.gt2_drpwe (1'b0),
.gt2_drpdo (),
.gt2_drprdy (),


.gt3_drpaddr (9'd0),

.gt3_drpdi (16'd0),
.gt3_drpen (1'b0),
.gt3_drpwe (1'b0),
.gt3_drpdo (),
.gt3_drprdy (),

// Tie off Tx Ports
// Lane 0
.gt0_txdata (32'b0),
.gt0_txcharisk (4'b0),

// Lane 1
.gt1_txdata (32'b0),
.gt1_txcharisk (4'b0),

// Lane 2
.gt2_txdata (32'b0),
.gt2_txcharisk (4'b0),

// Lane 3
.gt3_txdata (32'b0),
.gt3_txcharisk (4'b0),


// Rx Ports
// Lane 0
.gt0_rxdata (gt0_rxdata),
.gt0_rxcharisk (gt0_rxcharisk),
.gt0_rxdisperr (gt0_rxdisperr),
.gt0_rxnotintable (gt0_rxnotintable),

// Lane 1
.gt1_rxdata (gt1_rxdata),
.gt1_rxcharisk (gt1_rxcharisk),
.gt1_rxdisperr (gt1_rxdisperr),
.gt1_rxnotintable (gt1_rxnotintable),

// Lane 2
.gt2_rxdata (gt2_rxdata),
.gt2_rxcharisk (gt2_rxcharisk),
.gt2_rxdisperr (gt2_rxdisperr),
.gt2_rxnotintable (gt2_rxnotintable),

// Lane 3
.gt3_rxdata (gt3_rxdata),
.gt3_rxcharisk (gt3_rxcharisk),
.gt3_rxdisperr (gt3_rxdisperr),
.gt3_rxnotintable (gt3_rxnotintable),

// Serial ports
.rxn_in (rxn),
.rxp_in (rxp),
.txn_out (),
.txp_out ()
);

 

 

 

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Observer tyhero
Observer
758 Views
Registered: ‎06-15-2018

Re: JESD sync is wrong

Hi,

 

Is there something I need to be careful in the ip panel?

Please review the attached picture.

 

Best,

Hong

 

 

jesd_phy_issues.png
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