09-07-2016 03:13 AM
When I run the behavioural simulation of the JESD204 v7.0 core configured as 1-lane TX in Vivado2016.2 the testbench fails.
The JESD_PHY starts to go havoc during the 2nd multi-frame of the ILA Phase. Comparison with the data generated by the JESD protocol core shows that the core sends on the txdata bus "XX" for the 3rd and the 14th byte of the configuration data in the 2. MF, which corresponds exactly to the frame position where the PHY starts to fail. Evaluating various other configuration shows that the failure is persistent. I have attached screenshots of the simulator. The inputs of the JESD protocol core which correspond to the values which should be in these configuration bytes are set and stable.
The same example generated in Vivado2015.4 with the JESD204 v6.2. IP core simulates correct.
Has anyone else observed this problem and found a fix (except of downgrading to 6.2)?
09-08-2016 02:40 AM
Is this issue seen with the example design generated with the core or in your design simulation?
Can you attach the xci file if seen in example design.
09-08-2016 08:12 AM