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Visitor pice
Visitor
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Registered: ‎07-18-2017

JESD204 PHY txoutclk, rxoutclk 0.0 Hz, Tool and IP issue IP Version 4.0 Vivado 2018.1 & 2018.2

Dear Community,

 

this is more a Bug report than a question:

During IP Configuration of the JESD204_PHY the line rate (transfer speed per lane)  is not properly interpreted. If one gives an integer number like 10 the CONFIG.FREQ_HZ of txoutclk and rxoutclk is set to 0.000 Hz.

This leads to the following tooling issues:

o Timing Report after Synthesis is running in an endless loop without any errors or warnings.

o Implementation is also hangs and does not complete. ( Also no warnings and errors )

If one gives an 10.0 as number everything is fine.

 

Version <4.0 of JESD204_PHY interprets the integer number correctly .

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Moderator
Moderator
360 Views
Registered: ‎01-16-2013

Re: JESD204 PHY txoutclk, rxoutclk 0.0 Hz, Tool and IP issue IP Version 4.0 Vivado 2018.1 & 2018.2

@pice

 

Thanks for reporting! We are aware of this issue and it will be fixed in the future release of Vivado. Please check the following forum link for the workaround:

https://forums.xilinx.com/t5/Networking-and-Connectivity/JESD204B-PHY-clock-pins-assigned-incorrect-FREQ-HZ-value-in-2018/m-p/880197

 

--Syed

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