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Observer chuffine@cai
Registered: ‎07-30-2018

JESD204 Pipelining registers

How can I add pipeline registers to the JESD204 core? When I look at the example, there are IBUF blocks in front of all the signal inputs, the user's guide specifically says to register the inputs and outputs for better performance, and the 3rd party example design I have has flip flops inserted before every signal, so I believe that these are important. My question is simply HOW do I get these flip flops or buffers in place? I spent two hours googling and I haven't found much discussion on how to pipeline registers in the Vivado IP integrator.

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