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Observer s381168
Observer
7,716 Views
Registered: ‎02-09-2013

JESD204 Reset in Zynq

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Hello,

I am using Zynq 7045 SOC.

 

I have instantiated my JESD204 core, however when reading back the Reset register, the block appears to be in reset and never leaves reset.

I know I can read and write this reset register (offset 0x4) because I can set the 'disable watchdog' bit.

Any idea why the core would be held in reset?

 

I've attached the tx_reset input signal to an inverted version of my PL reset signal from the Zynq.

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1 Solution

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Xilinx Employee
Xilinx Employee
14,243 Views
Registered: ‎08-13-2013

Re: JESD204 Reset in Zynq

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I'm assuming that you have simulated the design successfully.

I'd start by confirming all the 'Hardware Debug' general checks are met. This is also in PG066. In particular check that the QPLL/CPLL in the transceiver is locked.

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Xilinx Employee
Xilinx Employee
7,639 Views
Registered: ‎08-13-2013

Re: JESD204 Reset in Zynq

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What is the version of the core you are using?
I'd start by verifying that the GTX is coming out of reset.
The JESD204 core is held in reset until the transceiver has completed its own reset. The txresetdone pin from the GT can be observed if you enable the optional transceiver debug ports.
Observer s381168
Observer
7,605 Views
Registered: ‎02-09-2013

Re: JESD204 Reset in Zynq

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Using 6.0.
How long should the transceiver reset take? I'm waiting seconds.
What would cause the transceiver to not complete its reset?
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Xilinx Employee
Xilinx Employee
14,244 Views
Registered: ‎08-13-2013

Re: JESD204 Reset in Zynq

Jump to solution

I'm assuming that you have simulated the design successfully.

I'd start by confirming all the 'Hardware Debug' general checks are met. This is also in PG066. In particular check that the QPLL/CPLL in the transceiver is locked.

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