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Adventurer
Adventurer
425 Views
Registered: ‎01-18-2012

JESD204 Simulation speed

Hello Xilinx World,

 

I am simulating 2 JESD204 IP (RX an TX) using vivado 2018.2.

The gt_reset_done signal goes high after around 2.3 ms, wich correspond to 15H of running simulation on my computer...


Is it possible to accelerate de simulation speed???

I know it was possible with some others IP by setting a PROPERTY to true before genrating the block design.


Thank you for your help.

 

Best regards

 

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Xilinx Employee
Xilinx Employee
379 Views
Registered: ‎10-19-2011

Re: JESD204 Simulation speed

Hi @mlefevre,

 

what device/GT are you actually using? Do you simulate with the GTs or just the JESD cores?

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Adventurer
Adventurer
367 Views
Registered: ‎01-18-2012

Re: JESD204 Simulation speed

Hello,

 

I am using GTYE4 on xcvu9p.

I am simulating with GTs (waiting for gt_reset_done).

 

I 'am simulating 2 block design :

  • 1 containing a 8 Lane jesd204 Rx core and a JESD204 phy
  • the others containing a 8 Lane jesd204 Tx core and a JESD204 phy

Both block design are connected together (SERDIN/SERDOUT and syncB) in a Test Bench to simulate the interface with a JESD204 ADC.

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