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Visitor
Visitor
7,861 Views
Registered: ‎03-06-2015

JESD204 v6.0 problem clocking and buffers

 
Hi,
 
I am working with the development kit VC707 and an ADC card from Analogic Devices (AD9656EBZ) using VIVADO suite 2014.3  . This card uses JESD204B and I am trying to implement it on my project, however, I have some problems using the JESD204 IP core v6.0.
As I understood, I can choose between the shared logic in core or in example design but, as I saw, choosing the easiest way to use the IP core (selecting shared logic in core) we need to insert a clock from outside of the card like , for example, a clock generator. In my case, I am not interested on this, I would like to use a internal clock from the fpga for the refclk and the others.
I have been watching also the option of choosing shared logic in example design. But, the problem now is that to use it I need to use the Transceiver wizard for the GTX due to the state of pre-production of the JESD204-PHY IP core v1.0.

I would like to use the JESD204 IP core with the following parameters in bold from the table:

Number of Lanes (L)

2

2

4

Number of ADC (M)

2

4

4

K = frames per multiframe

Ceil(17/2)=9 => 12(multiple of 4)

ceil(17/4)=5 => 8(multiple of 4)

ceil(17/2)=9 => 12(multiple of 4)

F =(2*M)/L  octets per frame

2

4

2

Device Clock

125 MHz

125MHz

125MHz

ByteClock=DeviceClock*F

250MHz

500MHz

250MHz

Serial Line Rate=Byteclk*10

2.5Gbps

5Gbps

2.5Gbps

Coreclock=Byteclk/4=SLR/40(= glblclk)

62.5MHz

125MHz

62.5MHz

Refclk (=2*glblclk)

125MHz

250MHz

125MHz

F*K

2*12=24

4*8=32

2*12=24

SYSREF=Coreclk/(F*K)

2.6042MHz

3906250 Hz

2.6042MHz

I have tried to use a clock from the clocking wizard as the refclk and the glblclk of  the JESD204 IP core  but I had problems saying that was a routing violation and I tried to investigate a little bit and it came form the different buffers included in the IP core for the clocks. In the following images you can see the buffers I have mentioned inside the shared clocks.

Imágenes integradas 2
 

So more or less, my questions could be resumed by the followings:
-Which is the best option if I want to use an internal clock from the FPGA that is the output from a clocking wizard or another block? How should I route it?
-In case that I can not use the JESD204 IP core with the shared logic in core, which blocks should I include apart from the Transceiver Wizard? How should I configure it?

Thanks for all and sorry if do not explain myself correctly.
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Highlighted
Visitor
Visitor
7,756 Views
Registered: ‎03-06-2015

These are the errors I had using the clocking wizard to implement the clocks needed for the JESD204 IP core with the buffers.

 

 https://gm1.ggpht.com/1WRJ3X6Zwwnn48nRYdImu7RFay3gq3wGJ-goo17CszHitd7hlp0K98YuZL-dRBpKKy4dRJlcdEQ_lWlHz2DW5qvZsdT6sk89yguhcbZXBWRx3JN0430nYFb_KEKGoeAIKB_ge5Q9YuAyBX32GDu6wrSvh7QCsSsjshZr__ysRFs9OnI-vAMsk_snXFQTzbSM4Ibw4im75ZeFTA2jLl28vfH1tVHg2j948L8J66yxUvN1EH8rr8msH8vgNsTAIGvm50BJOa30iJ9PeroPo-s-HlottKPToM8010COTQ6oCuiKWlmyyzrsLsnDgLwgzDQup1bHbCHzKFjY9qOIuUY6yF0rJoOBXklwbeoPfGcDmw1JHhxpksMZvgV2dKmqpYL9JPsWzSv4D55PpYD818MnZLbm0m9xVBcZ-xETVKHkZmKY-JSy5LQ_fWi6ZlGcGCmhIg4dx7UYAJqtsj_i_u_ScBSKrmzBjVdWu25bhMwNIHEXo97fM27WQpyFmV7OjCc1O2hweh8somGL0nH9lMc3AfYQGATsBK6Ary2ZlHGfn5mfiEcF_PBciBw-d4DLp8nXWrs6=s0-l75-ft-l75-ft

As I see, I have these errors (with the codes REQP-61, REQP-62 and REQP-1619) because i am not using/connecting well the mmcm and the ibufs to the JESD204 IP. How should I do to connect an internal clock to the JESD204 IP core?

 

Thanks!

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Xilinx Employee
Xilinx Employee
7,746 Views
Registered: ‎02-06-2013

Hi

 

Are you trying to drive the reference clocks to the GT from the internal MMCM.

 

You should drive this clock from a external oscillator.

 

Also paste the full error messages.

Regards,

Satish

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