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Participant
Participant
3,004 Views
Registered: ‎03-16-2014

JESD204B core pin swap

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Hi,

 

I have an DAC with 8 JESD204B TX lanes. The can be programmed to map the lanes arbitrarily.  That is you can swap around the lanes within the DAC.

 

Using the Xilinx JESD204B IP core can I also configure it to receive different lanes from different Quads arbitratily.

 

More clearly assume I use only two lanes instead of 8. LANE_0 carries DATA_0 and LANE_1 carries DATA_1.  Say in my working design LANE_0 is mapped to MGT_QUAD_A_RX0 and LANE_1 to MGT_QUAD_A_RX1 .

 

I now configure the DAC to swap the lanes. So DATA_0 is sent over LANE_1 and DATA_1 is sent over LANE_0. Now MGT_QUAD_A_RX0  recieves DATA_1 MGT_QUAD_A_RX1 receives DATA_0.  Can I just get this scenario working as well?  If yes, iIs it just by altering the XDC? Or the JESD204B configuration?  And again if yes will it work for possible mappings of the 8 lanes?

 

Thanks

 

 

 

 

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Xilinx Employee
Xilinx Employee
4,962 Views
Registered: ‎08-01-2008
yes you just required to change in XDC file and make sure lanes in use parameter set it correctly . Please refer 2-25

https://www.xilinx.com/support/documentation/ip_documentation/jesd204/v7_1/pg066-jesd204.pdf
Thanks and Regards
Balkrishan
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Xilinx Employee
Xilinx Employee
4,963 Views
Registered: ‎08-01-2008
yes you just required to change in XDC file and make sure lanes in use parameter set it correctly . Please refer 2-25

https://www.xilinx.com/support/documentation/ip_documentation/jesd204/v7_1/pg066-jesd204.pdf
Thanks and Regards
Balkrishan
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Participant
Participant
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Registered: ‎03-16-2014

 Thanks @balkris,

 

And as far as I understand it is even possible to swap the RX_N and RX_P pairs as well right?

 

For example (this time for an ADC), if on the PCB the

 

LANE0_N is routed to FPGA MGT_RX0_P pin and

LANE0_P is routed to FPGA MGT_RX0_pin I can even configure my MGTs to compensate for that to correct the data for the JESD204B core to work correctly. Can you also confirm this?

 

Thx

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Xilinx Employee
Xilinx Employee
2,925 Views
Registered: ‎02-06-2013

Hi

 

When you enable transceiver debug ports while core generation then you can find gtn_txpolarity and gtN_rxpolarity ports at the top level which you can use to control the polarity.

 

Setting this to 1 will reverse the polarity.

 

 

Regards,

Satish

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