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Visitor
Visitor
10,251 Views
Registered: ‎04-12-2016

JESD204B stuck in reset

I'm working on a system that uses the KCU105 with an Analog Devices ADC. I have a JESD PHY 3.0 core connected to a JESD 6.2 core.

 

In this system I need to be able to change the line rate of the JESD serdes. In doing so I need to reset the ADC, which causes the JESD CPLL to lose lock.

 

I'm having a problem where raising and lowering the RX_SYS_RESET (both as an input to the IP and through the AXI registers) does not reliably cause the JESD PLL to relock, and as a result the JESD IP does not leave reset. This also happens when raising and lowering the rx_reset input to the JESD IP.

 

It can take 5-10 tries, no matter which control signal I use, in order to get the PLL to lock. This, coupled with some amount of delay to give the PLL time to settle before retrying, ends up taking up to 350ms to get the JESD core out of reset.

 

Could anyone give insight as to why this is happening? Is it expected to take that long to switch the line rate?

 

Thank you.

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Moderator
Moderator
9,556 Views
Registered: ‎07-23-2015

Moving to the right board to get visibility and responses

- Giri
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There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
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Xilinx Employee
Xilinx Employee
9,548 Views
Registered: ‎02-06-2013

Hi

 

Are you following the Line rate switching sequence mentioned in PG198

Regards,

Satish

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Visitor
Visitor
4,834 Views
Registered: ‎11-18-2016

Hi,
I'm facing very similar issue with Kinter Ultrascale. Symptoms are exactly the same.

Have you found any solution/cause to this issue?

Any help would be very appreciated.

best regards

Petr
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