04-12-2016 02:31 PM
I'm working on a system that uses the KCU105 with an Analog Devices ADC. I have a JESD PHY 3.0 core connected to a JESD 6.2 core.
In this system I need to be able to change the line rate of the JESD serdes. In doing so I need to reset the ADC, which causes the JESD CPLL to lose lock.
I'm having a problem where raising and lowering the RX_SYS_RESET (both as an input to the IP and through the AXI registers) does not reliably cause the JESD PLL to relock, and as a result the JESD IP does not leave reset. This also happens when raising and lowering the rx_reset input to the JESD IP.
It can take 5-10 tries, no matter which control signal I use, in order to get the PLL to lock. This, coupled with some amount of delay to give the PLL time to settle before retrying, ends up taking up to 350ms to get the JESD core out of reset.
Could anyone give insight as to why this is happening? Is it expected to take that long to switch the line rate?
04-28-2016 02:29 AM
Moving to the right board to get visibility and responses
04-28-2016 03:29 AM
Are you following the Line rate switching sequence mentioned in PG198
11-18-2016 06:41 AM