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Participant deepwavebill
Registered: ‎08-09-2018

JESD204B sync only possible if .bit file is loaded after the core/ref clocks are enabled

I have the same problem that other users of the JESD204B TX, RX, and PHY cores have reported in that the JESD204B bus only achieves sync if the core and ref clocks are enable before the .bit file is loaded into the FPGA.

We are using a AD9371 transceiver and the AD9528 to generate the SYSREF, core clk, and ref clk. I am using an Artix 7 75 device and we have 4 JESD204B lanes in both directions.

I have a block design which instantiates two each of the JESD204B TX and RX cores, two lanes each. I have also implemented two JESD204B PHY cores, two lanes each. I have a common clock generation logic block which generates the ref clk and core clocks.

I tried using the MMCM_lock signal, inverted, as a reset signal to the TX and RX JESD204B cores, but I stil cannot get good link status for the JESD204B TX or RX cores. Any other suggestions would be greatly appreciated. 

I am happy to send you my design if that helps.




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