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Observer
Observer
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Registered: ‎01-31-2018

Jesd204b subclass rx_sync

100MHz10dBm인가 1기가샘플링 axi_rx_tvalid에 래치된 것과 래치 안된 데이터.pngHello
I am using Virtex7 for designing jesd204b subclass0 RX to get ADC data from ADC.
I suceeded getting ADC result.
But the data has discountinous region like having noise.
I think rx_sync is the cause. After initializing jesd204b interface, rx_sync should be high. But the signal of rx_sync comes back to low.
So the digital data looks like having noise.
Plz help me, give me an advice
L=2, link rate=10Gbps,k=32,F=1, I am using jesd204 ip & jesd204 phy serially ,LMFC buffer size 1024byte, sysref off, scramble on(same as ADC condition).

I am latching ADC data like as below

 

always @(posedge core_clk)

if(rx_tvalid&&rx_sync)

ADC data <= {~~~~~~};

else

ADC data <= ADC data;


How can i make rx-sync stable high?

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