07-07-2020 11:01 AM
Hi, for my project I wan to connect data from PC via ethernet and output the data via SFP. The data is received in ethernet protocol and data output without ethernet protocol.
I have a block diagram design using the IP integrator tool in vivado but it's having errors.
Can you guys help me fix my design?
I first used the TEMAC CORE to receive data. Then the received data is sent to FIFO to accommodate the latency of different components.(If there a way to directly connect the 2 MAC's, let me know). I then connect the TX and RX transmitter. The TX transmitter then transmits the receive data to the TEMAC IP. Which then send the data to he PCS/PMA or SGMII IP to output data through SFP+. No data manipulation is required, just simple data transfer. AXI4 lite is used to control the MAC's. I think AX4 lite IP contains the configuration data for the MAC and PHY. All the IP's are taken from Vivado IP catalog.
Error I get :
07-08-2020 03:17 AM - edited 07-08-2020 03:21 AM
Thanks, but the purpose of the post is to help me validate my architecture pertaining to my application. Can you validate my design architecture.
PC -> ethernet port via copper cable -> FPGA -> SFP+ -> optical fibre
The input data rate from PC to FPGA and output data rate from FPGA to SFP+ is same, ie 1Gb/s.
Q1. Do I need to add FIFO's between 2 designs? I guess so since the two MAC cores are different, one for ethernet while the other for SFP+ cage.
Q2. How do you configure the PHY'S and MAC for simple data transfer? I see everywhere it's written about MAC and PHY config registers but no where how to o them. Doesn't the TEMAC cores do the default configs themselves. I don't want to use microblaze to configure the MAC's