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galactic
Observer
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Registered: ‎11-01-2019

KSZ9563R 3 Port Switch, transmit working no receive

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I am working on integrating a KSZ9563R switch onto a Zynq-Ultrascale+ device on the GEM3 MIO module. From my understanding this switch connects to the zynq in a MAC->MAC "direct-link" fashion, no MDIO pins are used (instead there is a standalone I2C interface).

The goal was to have the switch configured and operating in an un-managed state on start-up using its strapping resistors, but I discovered that in RGMII control registers for this device, a bit still needs to be set by the host processor over a serial connection (In this case I2C) it was the following: 

RGMII Ingress Internal Delay (RGMII_ID_ig)
1 = Minimum 1.5 ns delay is added to ingress RGMII clock

In the end I want this switch to integrate with xilinx u-boot and a petalinux kernel but as a stepping stone I have been using lwIP in the xilinx SDK. Using a modified version of lwIP to support direct link as shown here (https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841998/Testing+Fixed+Link+support+in+U-Boot) and using the echoTCP xilinx test application, I have successfully observed over wireshark a DHCP request message, followed by DHCP offer from my server, there is no acknowledge from the xilinx module, leading me to believe that the board is not receiving packets. 

Because the referenced guide shows a different version of lwIP then what I'm using I had to make one additional change to get it this far, here the changes I made to the lwIP xilinx driver:

/lwip211_v1_0/src/contrib/ports/xilinx/netif/xadapter.c/lwip211_v1_0/src/contrib/ports/xilinx/netif/xadapter.c/lwip211_v1_0/src/contrib/ports/xilinx/netif/xemacpsif_physpeed.c/lwip211_v1_0/src/contrib/ports/xilinx/netif/xemacpsif_physpeed.c

I also included a function in the main that writes the RGMII Ingress Internal Delay bit to the RGMII control register. There is also a  RGMII Egress Internal Delay bit which is enabled by default, yes I tried disabling it and that caused it to stop transmitting, I wouldn't expect it to work in that state because it is my understanding there needs to be some delay on the lines to get the sampling correct on either end. I also tried setting the connection to lower speeds (10Mb/s and 100Mb/s) which produced no difference. 

My next step was to try and test the RGMII delay on the receive lines using a method similar to the once described in the TI attachment, I do not have a TI phy/switch but I am referencing it to continue debugging. I'm not sure if this is a layout issue yet or just something in lwIP I am missing, any guidance from here would be great! I need to find some kind of TCP echo and/or bit blaster client that floods the switch with Ethernet traffic so I can see how it is received on the RGMII line. 

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galactic
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Registered: ‎11-01-2019

Fixed, there was an error in the KSZ9563 rev C data sheet, corrected in rev D. I had to disable in-band status mode to allow fixed link MAC->MAC mode work properly. 

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galactic
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Registered: ‎11-01-2019

Fixed, there was an error in the KSZ9563 rev C data sheet, corrected in rev D. I had to disable in-band status mode to allow fixed link MAC->MAC mode work properly. 

View solution in original post

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