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Visitor
Visitor
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Registered: ‎09-29-2020

Kintex-7 10G-Ether PHY: About sharing coreclk and txuserclk

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I think that it is as described in Figure 3-23: of PG068.
I use two PHYs in the GT_QUAD  , is it possible to use the coreclk and txuserclk generated by one PHY in the other PHY?
However, the reset of the two PHYs should be the same.

However, the reset of the two PHYs should be the same.

See:
PG068: Figure 3-23: Attaching Multiple Cores to a GT_QUAD Tile Using the Shared Logic Feature

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Adventurer
Adventurer
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Registered: ‎03-21-2011

Just as an aside:  It's amusing that the intern Xilinx gave the job of creating the master block's schematic symbol was apparently to introverted to walk down the hall to talk to obviously the OTHER intern you assigned the slave block's symbol to.  Thus leading to that wonderful zig-zag wiring diagram on almost-but-not-quite aligning symbols.  So close.  Yet missed it by a hair.  Goodby nice clean, satisfying, 1:1, fully horizontal wires.

Also, shouldn't something drive areset_coreclk?

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @mam-suzuki1 

Yes, that is possible,
Just generate one IP as a master IP (==Include Shared logic in core)
and other IP as a slave IP (==Include Shared logic in example design),
and connect the clock from master IP to slave IP as follow.

Master_Slave_10G_ET_PCSPMA_IP_con.png

Please generate an example design for both IP configuration to get a reference on how to connect each signals.

Thanks & regards
Leo

Visitor
Visitor
494 Views
Registered: ‎09-29-2020
Hi Leo
Thank you for wearing an easy-to-understand diagram.
Adventurer
Adventurer
457 Views
Registered: ‎03-21-2011

Just as an aside:  It's amusing that the intern Xilinx gave the job of creating the master block's schematic symbol was apparently to introverted to walk down the hall to talk to obviously the OTHER intern you assigned the slave block's symbol to.  Thus leading to that wonderful zig-zag wiring diagram on almost-but-not-quite aligning symbols.  So close.  Yet missed it by a hair.  Goodby nice clean, satisfying, 1:1, fully horizontal wires.

Also, shouldn't something drive areset_coreclk?

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Visitor
Visitor
408 Views
Registered: ‎09-29-2020

Hi bitjockey
Thank you for answer.

 

A figure doesn't have areset_coreclk of a slave side but it connects areset_coreclk output from a master.

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