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Participant typhoonwa
Registered: ‎06-09-2010

LBUS protocol rules

Hi all,

    I'm seeing a behavior on the LBUS protocol used on the 100G CMAC IP which I can't quite classify as invalid or not based on what's being included in the guide (PG203).

If you look at the attached screen shot you'll see I'm getting a two cycle long SOP. The first of these cycles is invalid since only the enable signal for segment 2 is asserted. In the 2nd cycle however the enable for segment 0 is asserted. Is this a valid cycle or not? The guide is not explicit on this, though my guess is that it isn't. Is this assessment correct?

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Visitor hoven
Registered: ‎01-29-2015

Re: LBUS protocol rules

The first clock cycle with SOP0=1 is illlegal since segment 0 must have data if any segment has data ("Bus Rules" in page 62).

Several other clock cycles are also illegal since they have ENAOUT set for some segments but not for segment 0.

PG203 states in table 2-4 that SOP should only be used when ENAOUT is 1 (in the same segment). This means that the second SOP cycle is a valid SOP for segment 0, but the clock cycle is illegal anyway since segments 1-3 are Idle. As I understand it, no Idle segment is allowed inside a packet unless all segments are idle in that clock cycle. Also, a minimum length packet needs data in 4 segments.


 I have another case that isn't listed as legal or illegal in any example in tables 3-4 or 3-5. It is legal to have "Idle" in the segment(s) after EOP in a clock cycle. It is also legal to have SOP in the segment immediately after a EOP segment.

The missing case is the sequence "EOP Idle SOP" or "EOP Idle Idle SOP" in one clock cycle.

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