09-15-2020 12:50 AM
We have a MicroBlaze-based product running on VIRTEX 7 using LWIP. we are running the LWIP TCP perf server and LWIP TCP perf client in SDK 2019.1 on the custom board (XC7VX550T-2FFG1927I), But we are getting only 40Mbps to 50Mbps Throughput for 1G EThernet (RGMII Phy 88E1512 ).
I have tried the LWIP UDP perf server and UDP perf client, in both cases again speed was 10Mbps to 20Mbps in SDK 2019.1.
In the Vivado block design, we have added a 1G ethernet subsystem (RGMII) IP with the DMA controller. Also, we are using MIG IP for DDR3 memory.
I am adding an RTL Block diagram for your reference :
Then we tried on Artix 7 Evaluation board ac701. We used the RTL and Hardware description file(HDF) from the Xilinx website :
But Still, we get the 29Mbps speed on Artix 7 board using the same example code from SDK 2019.1.
Kindly suggest solutions to resolve this issue.
09-24-2020 02:46 AM
We have ported the Petalinux on Artix-7 evaluation board Ac-701 with Iperf2 and Iperf3.
We tested the Ethernet Throughput with both versions of Iperf, and it is coming around 11Mbps. We are not getting what is the issue. Kindly help us to resolve this issue.
Thanks & regards
Devendra Pundir
10-19-2020 06:50 AM
Hi @pundir241 ,
LwIP parameters need to be tuned for the best performance. You can check UG1137 for details of lwip settings:
https://www.xilinx.com/support/documentation/user_guides/ug1137-zynq-ultrascale-mpsoc-swdev.pdf
For Linux testing, have you used the provided BSP? If not, would you please test that first and see if that shows differently?
10-22-2020 03:59 AM
Hi @nanz
I have configured the LWIP in its best performance and I tested on Zedboard and it is working and getting throughput of 980Mbps but when I am working on Virtex 7 or Artix 7 board then we are getting throughput of 20-30Mbps only. The Only difference I able found in these two conditions that Zedboard (zynq-7000) is having a hardcore Arm processor and hardcore ethernet mac but whereas in Virtex-7 or Artix -7 is a soft-core processor (Microblaze) and softcore AXI-ethernet mac. So what I am thinking that we are missing something in block design configurations.
And for Linux testing, we are using Provided PETALINUX BSP from Xilinx.
Thanks & regards
Devendra Pundir