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Visitor apiskur
Visitor
468 Views
Registered: ‎01-16-2019

LWIP UDP Communications Not Working on ZCU-102 A53 Cores 2 and 3

Hello,

I was wondering if anyone has run into this particular problem, or could possibly help me find a solution.  I am developing a baremetal application for a ZCU-102 that communicates with another application running on a PC.  I have been partially successful in using the LWIP raw UDP functionality of the Xilinx SDK's board support package.  The application I have developed communicates just fine if I load it into cores 0 or 1 of the A53 processor in the ZynqMP on the eval board.  If I take the exact same application and load it onto cores 2 or 3 of the A53 processor, it ceases to be able to communicate via UDP.  Activating debug statements in the LWIP, via the BSP, produces no useful information. 

As a sanity check, I loaded the UDP perf client example program from the SDK onto my ZCU-102, on A53 core 2 and ran the server component on my PC.  The UDP perf client will not initiate the conversation when running on core 2 or core 3.  It works a lot better on core 0 or core 1. 

Has anyone experienced this before?  I am using the Xilinx SDK version 2018.2.  I am using the default example FSBL and default ZCU-102 hardware profile.  Whether I program QSPI or load via jtag makes no difference.  

 

Thanks.

 

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Visitor kgraefe
Visitor
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Registered: ‎08-21-2019

Re: LWIP UDP Communications Not Working on ZCU-102 A53 Cores 2 and 3

Did you ever solve your problem? I I think I may have the same issue.

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Visitor apiskur
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Registered: ‎01-16-2019

Re: LWIP UDP Communications Not Working on ZCU-102 A53 Cores 2 and 3

Thanks for your reply.  We decided to go with serial port communications for our applications that we run in single-core mode on cores 2 and 3.  We have been very successful with this kind of setup using the baremetal OS configuration.

I read your question and the replies to it, and that is basically the response I got from talking with Xilinx representatives directly.  They do not officially support running ANYTHING on cores 2 and 3 of the A53 in the Ultrascale+ SOC.  The whole AMP argument arises whenever I mention cores beyond core 0 of the A53.  I did not attempt to chase the problem any further after learning this.  I will not, however, close this topic as I believe Xilinx needs to enable single core operation on all cores of the A53, at least with a single baremetal application and no other cores in use.  The fact that core 0 and core 1 both work this way means somebody neglected to get cores 2 and 3 functional in the same manner.     

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