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Participant isaakian
Participant
187 Views
Registered: ‎07-03-2013

LWiP on FreeRTOS (2018.3 vivado) GEM3 and APU3 will not process Ethernet Packets (ZYnq MPSoC)

Similar to an prior bug I found where the BSP does not correctly setup IRQ steering to CPUs[2,3] on the MPSoc;  Our system uses a seperate application on each APU[0..3], each with LWiP and FreeRTOS, and each using a seperate GEM[].

 

APU[0,1,2] all work after fixing the prior bug with the RTOS Tick IRQ not getting mapped from the GIC Target registers to CPU[2,3].  However CPU[3] still would not process packets. 

 

Tracing down the issue:

GIC Interrupt 95 is GEM3:
IRQ Name | IRQ Number | GICPx_IRQ Bits | (GIC Proxy) Description
GEM3      | 95 GICP1  | [31]           | Ethernet 3 controller

GICD_ISENABLER2 Bits[30] Enables ISR #95 to the Distributor from the GEM:
0xF9010108 => 0x80000010
Seems OK
 
 
<<< NOTE For some reason you have to use Expressions in xsdk to read these registers:
Create new Expression -> *(volatile unsigned int*) 0x0000F901085C>>>
GICD_ITARGETSR23 Bits[31:24] is the Distributor steering register for this IRQ:
0xF901085C => 0x04040404

This is mapping IRQ[95,94,93,92] => CPU #2  This is wrong....

Changing Bits[31:24] => 0x08 (Map to CPU#3 and now LwiP runs, responds to PING etc.
 
So if you want to run seperate apps on each CPU with different GEMs you may have to make the same fix. 
 
 
Digital Design Golden Rule: If its not tested - its broken.
2 Replies
Moderator
Moderator
99 Views
Registered: ‎08-25-2009

Re: LWiP on FreeRTOS (2018.3 vivado) GEM3 and APU3 will not process Ethernet Packets (ZYnq MPSoC)

Hi @isaakian ,

Thank you for your post. When I read it, is it more of bug found and report issue for Xilinx? If so, would you be able to provide a test case so that I could reproduce the issue on my end? Have you tested with 2019.1/2 Vivado?

 

"Don't forget to reply, kudo and accept as solution."
Participant isaakian
Participant
79 Views
Registered: ‎07-03-2013

Re: LWiP on FreeRTOS (2018.3 vivado) GEM3 and APU3 will not process Ethernet Packets (ZYnq MPSoC)

Hi Nanz,

Yes, it's a bug report and solution both to help Xilinx and anyone else who runs into the same issue.

I have not tested on 2019.1/2 yet, but I looked at the latest driver (BSP) code from xSDK (2019.2) and I dont see any changes that would have fixed this. 

To recreate bug:

1. Create a BSP project and asign it to CPU#3 (A53 APU core 3) and associate it with the GEM3 (TEMAC3)

2. Create a app project using that BSP, and create demo LWiP project TCP/IP Echo server.  

This would show both IRQ bugs I believe.  

Digital Design Golden Rule: If its not tested - its broken.