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Observer disa
Observer
13,165 Views
Registered: ‎01-17-2014

MGT clocking and SI5324

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Hi,

 

As far as I was able to figure out, clock for MGT and 10GBASE module (VC709 board) should come from the output of the jitter attenuator SI5324. In one of the posts on this forum, it was suggested to use the attenuator in the free run mode, i.e. to use the 114.285 MHz oscillator to generate 156.25 Mhz MGT clock. However, in VC709 TRD and SI5324 example design, the attenuator is used with clock inpiut CKIN1 connected to the clock generated by user clock oscillator of 156.25 Mhz. 

 

1) Which mode should I use for my application? I will use SFP optical link, so I do not need synchronous transfer.

 

I tried running the SI5324 in the free run mode and setting up the registers according to the values from DSPLLsim, but the output frequency is just not correct.

 

2) Is there something else that I should do, but I am missing? Does someone have the correct, working values for the SI5324, to double check? I am using microblaze instead of picoblaze, and I2C control is operating properly.

 

Thanks a lot.

 

Vladan

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Adventurer
Adventurer
22,407 Views
Registered: ‎09-02-2014

Re: MGT clocking and SI5324

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I've  my own realization of I2C and configured SI5324 using configure tool.

 

It's a part of my code  with configurating si5324 registers. byteAddrArr is an array of register addresses, dataArr is an array of necessary values 

 

	byteAddrArr[ 0] <=   0;		dataArr[ 0] <= 8'h54;    //	00
	byteAddrArr[ 1] <=   1;		dataArr[ 1] <= 8'hE4;    //	01
	byteAddrArr[ 2] <=   2;		dataArr[ 2] <= 8'h42;    //	02
	byteAddrArr[ 3] <=   3;		dataArr[ 3] <= 8'h15;    //	03
	byteAddrArr[ 4] <=   4;		dataArr[ 4] <= 8'h92;    //	04
	byteAddrArr[ 5] <=   5;		dataArr[ 5] <= 8'hED;    //	05
	byteAddrArr[ 6] <=   6;		dataArr[ 6] <= 8'h2D;    //	06
	byteAddrArr[ 7] <=   7;		dataArr[ 7] <= 8'h2A;    //	07
	byteAddrArr[ 8] <=   8;		dataArr[ 8] <= 8'h00;    //	08
	byteAddrArr[ 9] <=   9;		dataArr[ 9] <= 8'hC0;    //	09
	byteAddrArr[10] <=  10;		dataArr[10] <= 8'h08;    //	0A
	byteAddrArr[11] <=  11;		dataArr[11] <= 8'h40;    //	0B
	byteAddrArr[12] <=  19;		dataArr[12] <= 8'h29;    //	13
	byteAddrArr[13] <=  20;		dataArr[13] <= 8'h3E;    //	14
	byteAddrArr[14] <=  21;		dataArr[14] <= 8'hFF;    //	15
	byteAddrArr[15] <=  22;		dataArr[15] <= 8'hDF;    //	16
	byteAddrArr[16] <=  23;		dataArr[16] <= 8'h1F;    //	17
	byteAddrArr[17] <=  24;		dataArr[17] <= 8'h3F;    //	18
	byteAddrArr[18] <=  25;		dataArr[18] <= 8'hA0;    //	19
	byteAddrArr[19] <=  31;		dataArr[19] <= 8'h00;    //	1F
	byteAddrArr[20] <=  32;		dataArr[20] <= 8'h00;    //	20
	byteAddrArr[21] <=  33;		dataArr[21] <= 8'h03;    //	21
	byteAddrArr[22] <=  34;		dataArr[22] <= 8'h00;    //	22
	byteAddrArr[23] <=  35;		dataArr[23] <= 8'h00;    //	23
	byteAddrArr[24] <=  36;		dataArr[24] <= 8'h03;    //	24
	byteAddrArr[25] <=  40;		dataArr[25] <= 8'h60;    //	28
	byteAddrArr[26] <=  41;		dataArr[26] <= 8'h9C;    //	29
	byteAddrArr[27] <=  42;		dataArr[27] <= 8'h39;    //	2A
	byteAddrArr[28] <=  43;		dataArr[28] <= 8'h00;    //	2B
	byteAddrArr[29] <=  44;		dataArr[29] <= 8'h16;    //	2C
	byteAddrArr[30] <=  45;		dataArr[30] <= 8'h37;    //	2D
	byteAddrArr[31] <=  46;		dataArr[31] <= 8'h00;    //	2E
	byteAddrArr[32] <=  47;		dataArr[32] <= 8'h16;    //	2F
	byteAddrArr[33] <=  48;		dataArr[33] <= 8'h37;    //	30
	byteAddrArr[34] <=  55;		dataArr[34] <= 8'h00;    //	37
	byteAddrArr[35] <= 131;		dataArr[35] <= 8'h1F;    //	83
	byteAddrArr[36] <= 132;		dataArr[36] <= 8'h02;    //	84
	byteAddrArr[37] <= 137;		dataArr[37] <= 8'h01;    //	89
	byteAddrArr[38] <= 138;		dataArr[38] <= 8'h0F;    //	8A
	byteAddrArr[39] <= 139;		dataArr[39] <= 8'hFF;    //	8B
	byteAddrArr[40] <= 142;		dataArr[40] <= 8'h00;    //	8E
	byteAddrArr[41] <= 143;		dataArr[41] <= 8'h00;    //	8F
	byteAddrArr[42] <= 136;		dataArr[42] <= 8'h40;    //	88

 In result, I've got 156.25 Mhz at ckout1.

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Xilinx Employee
Xilinx Employee
13,150 Views
Registered: ‎08-30-2011

Re: MGT clocking and SI5324

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Remember in Free run mode the XA/XB input is routed to CKIN2.  Make sure you're using CKIN2 and plugging in 114.285MHz to DSPLLsim - not 156.25MHz.  If you're getting a clock out but it's the wrong frequency, this may be the cause.

 

Jon

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Adventurer
Adventurer
22,408 Views
Registered: ‎09-02-2014

Re: MGT clocking and SI5324

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I've  my own realization of I2C and configured SI5324 using configure tool.

 

It's a part of my code  with configurating si5324 registers. byteAddrArr is an array of register addresses, dataArr is an array of necessary values 

 

	byteAddrArr[ 0] <=   0;		dataArr[ 0] <= 8'h54;    //	00
	byteAddrArr[ 1] <=   1;		dataArr[ 1] <= 8'hE4;    //	01
	byteAddrArr[ 2] <=   2;		dataArr[ 2] <= 8'h42;    //	02
	byteAddrArr[ 3] <=   3;		dataArr[ 3] <= 8'h15;    //	03
	byteAddrArr[ 4] <=   4;		dataArr[ 4] <= 8'h92;    //	04
	byteAddrArr[ 5] <=   5;		dataArr[ 5] <= 8'hED;    //	05
	byteAddrArr[ 6] <=   6;		dataArr[ 6] <= 8'h2D;    //	06
	byteAddrArr[ 7] <=   7;		dataArr[ 7] <= 8'h2A;    //	07
	byteAddrArr[ 8] <=   8;		dataArr[ 8] <= 8'h00;    //	08
	byteAddrArr[ 9] <=   9;		dataArr[ 9] <= 8'hC0;    //	09
	byteAddrArr[10] <=  10;		dataArr[10] <= 8'h08;    //	0A
	byteAddrArr[11] <=  11;		dataArr[11] <= 8'h40;    //	0B
	byteAddrArr[12] <=  19;		dataArr[12] <= 8'h29;    //	13
	byteAddrArr[13] <=  20;		dataArr[13] <= 8'h3E;    //	14
	byteAddrArr[14] <=  21;		dataArr[14] <= 8'hFF;    //	15
	byteAddrArr[15] <=  22;		dataArr[15] <= 8'hDF;    //	16
	byteAddrArr[16] <=  23;		dataArr[16] <= 8'h1F;    //	17
	byteAddrArr[17] <=  24;		dataArr[17] <= 8'h3F;    //	18
	byteAddrArr[18] <=  25;		dataArr[18] <= 8'hA0;    //	19
	byteAddrArr[19] <=  31;		dataArr[19] <= 8'h00;    //	1F
	byteAddrArr[20] <=  32;		dataArr[20] <= 8'h00;    //	20
	byteAddrArr[21] <=  33;		dataArr[21] <= 8'h03;    //	21
	byteAddrArr[22] <=  34;		dataArr[22] <= 8'h00;    //	22
	byteAddrArr[23] <=  35;		dataArr[23] <= 8'h00;    //	23
	byteAddrArr[24] <=  36;		dataArr[24] <= 8'h03;    //	24
	byteAddrArr[25] <=  40;		dataArr[25] <= 8'h60;    //	28
	byteAddrArr[26] <=  41;		dataArr[26] <= 8'h9C;    //	29
	byteAddrArr[27] <=  42;		dataArr[27] <= 8'h39;    //	2A
	byteAddrArr[28] <=  43;		dataArr[28] <= 8'h00;    //	2B
	byteAddrArr[29] <=  44;		dataArr[29] <= 8'h16;    //	2C
	byteAddrArr[30] <=  45;		dataArr[30] <= 8'h37;    //	2D
	byteAddrArr[31] <=  46;		dataArr[31] <= 8'h00;    //	2E
	byteAddrArr[32] <=  47;		dataArr[32] <= 8'h16;    //	2F
	byteAddrArr[33] <=  48;		dataArr[33] <= 8'h37;    //	30
	byteAddrArr[34] <=  55;		dataArr[34] <= 8'h00;    //	37
	byteAddrArr[35] <= 131;		dataArr[35] <= 8'h1F;    //	83
	byteAddrArr[36] <= 132;		dataArr[36] <= 8'h02;    //	84
	byteAddrArr[37] <= 137;		dataArr[37] <= 8'h01;    //	89
	byteAddrArr[38] <= 138;		dataArr[38] <= 8'h0F;    //	8A
	byteAddrArr[39] <= 139;		dataArr[39] <= 8'hFF;    //	8B
	byteAddrArr[40] <= 142;		dataArr[40] <= 8'h00;    //	8E
	byteAddrArr[41] <= 143;		dataArr[41] <= 8'h00;    //	8F
	byteAddrArr[42] <= 136;		dataArr[42] <= 8'h40;    //	88

 In result, I've got 156.25 Mhz at ckout1.

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Adventurer
Adventurer
13,133 Views
Registered: ‎09-02-2014

Re: MGT clocking and SI5324

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Also, I noticed, it's necessary to reset si5324 before configurating.

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Visitor kkugler
Visitor
10,934 Views
Registered: ‎06-25-2015

Re: MGT clocking and SI5324

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Thank you for putting up this information. I was also having trouble setting up the Si5324 in Free Run mode, but was able to use your settings to get it up and running.

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