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mvalvo
Adventurer
Adventurer
10,533 Views
Registered: ‎11-07-2007

MPMC

Hi, I'm using ISE 10.1 SP3, EDK, SDK.  all of my tools are up to date.  I'm using a V4FX100 fpga. I have an ISE design that instantiates XPS project.  I'm using a uBlaze processor and external DDR2 SDRAM. 

 

what works:  I added a MPMC to my XPS project.  The first port is for the plb,  the 2nd and 3rd are for the uBlaze XCL ports.  I made a simple program in SDK.  the program was executed from external memory successfully.

------------------------------------------------------- 

 

I added a 4th port to the MPMC; it's a NPI interface.  I want to access the DDR2 memory from logic located in my ISE project (outside of XPS).  I followed the directions and timing diagrams from the MPMC datasheet.  I made all of the PIM3## ports external so that they can be accessed by ISE.  I wrote some simple logic to write and read the memory through the NPI interface.  I chipscoped my design: I saw the init_done go high, I saw the addr_ack go high.  

 

what doesn't work:  I can't seem to verify that anything was written to memory.  the RdFIFO_empty signal is always high and my RdData signal is always zero.   Also, I tried to make the WrFIFO_almost_full signal go high, but i cannot. 

 

what am I doing wrong??  I tried to do single 32-bit writes and reads, and 8 32-bit writes and reads; neither of them work 

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11 Replies
emmount
Visitor
Visitor
10,469 Views
Registered: ‎03-11-2008

I'm having the exact same problem, with a Spartan-3A DSP.  Same port configuration; I'm happily running uCLinux out of SDRAM, but the NPI NPI_InitDone signal never goes high, and I get no response from NPI_AddrAck, when I bring my logic out of reset with a register bit and see it issue its first NPI_AddrReq.

 

Help!

 

- Eldridge

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jeremyk
Visitor
Visitor
10,013 Views
Registered: ‎01-14-2009

I'm using the NPI bus for my custom module in my EDK project and I'm experiencing the same problem. RdFIFO_Empty signal never goes low even after I request to read. I do however get the AddrAck signal after sending proper signals. I followed the timing diagrams from the MPMC data sheet exactly the way they were shown. Can someone please explain why RdFIFO_Empty signal stays high?
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mvalvo
Adventurer
Adventurer
10,008 Views
Registered: ‎11-07-2007

I got it to work eventually.  you really need to pay attention to the timing diagrams on the datasheet.  if you deviate from it, then weird things happen.  for example, it you try to read when the rdFifo is empty, then it will break.   hope this helps
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emmount
Visitor
Visitor
10,006 Views
Registered: ‎03-11-2008

I got things working as well... I now have lovely 480x272 24-bit video displaying a QT embedded GUI on our LCD!  Running PetaLinux on a MicroBlaze attached to all the video hardware.  My fundamental problem was a set of typos in my MPD file; looking at the generated top-level HDL source from XPS revealed that it was blithely ignoring the problem and just strapping everything off. :P

 

A word of caution that we discovered in the way of a video artifact until we squashed it - you *must* request addresses which are an integer multiple of the burst length you are requesting!  So, if you're bursting 32 32-bit words at a time from the NPI, your addresses must be aligned to a (4 bytes x 32 words = 128)-byte boundary.  If you give an address which is "in the middle" of a burst boundary, the controller will get to the next 128 byte boundary and then wrap back to the beginning of it (doing modulo addressing internally.)  This didn't seem to be documented anywhere in the MPMC user's manual.

 

As far as the timing goes, I just created a lightweight testbench module which mimics the behavior of the NPI and ran a unit simulation of my module against that.  Stuck to the sometimes-vague signal timing descriptions in the manual, and no problems.

 

- Eldridge

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jeremyk
Visitor
Visitor
9,977 Views
Registered: ‎01-14-2009

Guys, thank you so much for your replies. I realized that the clock source of the NPI_Clk input was connected to the 200MHz clock that the DDR uses. I corrected the problem, and the design works beautifully now. :smileyhappy:
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ascendere
Visitor
Visitor
7,882 Views
Registered: ‎02-03-2008

To which clock source the NPI must be conected?

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jeremyk
Visitor
Visitor
7,874 Views
Registered: ‎01-14-2009

Wow, I didn't expect to see any replies to this discussion after a year. Any ways, I believe the **bleep** I connected to was sysclk (100MHz).
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jeremyk
Visitor
Visitor
7,873 Views
Registered: ‎01-14-2009

That's strange.. How did the "bleep" get in there? It should read clock instead of **bleep**.
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jai_pandey
Participant
Participant
7,006 Views
Registered: ‎12-17-2009

Dear Mr. emmount

Thanks for your post. I am trying to capture video data stream coming from a camera, using the Xilinx ML-507 FPGA board. The data obtained is in RGB analog format, we have to display it on the VGA monitor. That design is working fine on ML507. We took the reference design from the VSK.

Similarly, for the same board we wish to buffer the captured frames in the DDR2 ( 32 bit data is being stored). After this we will retrieve the stored frames from the DDR2 and display it on the VGA monitor. The necessary IPs have been taken from the Video Starter kit design “DVI_Frame_Buffer_Demo” which is in UG 456(EDK Demonstrations/DVI_Frame_Buffer_Demo). The necessary changes in the C program and required changes for the PPC440 processor and have been done. We use the same IP's and use the same parameter settings as provided in the ref design. However we are getting garbage as output. If required. Please help me in this concern..

BR

Jai

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jai_pandey
Participant
Participant
2,900 Views
Registered: ‎12-17-2009

Dear Mr. emmount

Thanks for your post. I am trying to capture video data stream coming from a camera, using the Xilinx ML-507 FPGA board. The data obtained is in RGB analog format, we have to display it on the VGA monitor. That design is working fine on ML507. We took the reference design from the VSK.

Similarly, for the same board we wish to buffer the captured frames in the DDR2 ( 32 bit data is being stored). After this we will retrieve the stored frames from the DDR2 and display it on the VGA monitor. The necessary IPs have been taken from the Video Starter kit design “DVI_Frame_Buffer_Demo” which is in UG 456(EDK Demonstrations/DVI_Frame_Buffer_Demo). The necessary changes in the C program and required changes for the PPC440 processor and have been done. We use the same IP's and use the same parameter settings as provided in the ref design. However we are getting garbage as output. If required. Please help me in this concern..

BR

Jai

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eteam00
Instructor
Instructor
2,889 Views
Registered: ‎07-21-2009

You have responded to a thread which is about 18 months old.

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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