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Visitor
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Registered: ‎05-27-2014

MPSoC 10GE USXGMII support for MDIO / XAUI for AQV107/AQR107 PHY

It looks like all of the latest 10GE IP from Xilinx no longer has an MDIO to interface to external PHYs.  I have seen a few postings on the forums about using the XAUI interface's configuration / status vector mode.

https://forums.xilinx.com/t5/Ethernet/10G-Ethernet-MAC-missing-MDIO-port/m-p/851664

Does this work with the Marvell (Aquantis) AQR107/AQV107 PHYs?  (There was another post that indicated this was the route to use for the AQR107, I believe he AQV107 is the automotive version of this 10GE PHY).  Is this typically how 10GE wants to communicate this information that was handled in 10/100/1000 over MDIO?

Also, if they do use the USXGMII core (I think this was one mentioned as supporting this) are the Linux drivers (in this case, PetaLinux) there to support this interface or will they need to re-write these to get the status/control information over the XAUI interface?

Thanks,

Mark

 

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Registered: ‎04-01-2018

Re: MPSoC 10GE USXGMII support for MDIO / XAUI for AQV107/AQR107 PHY

Hi @sasten_avnet 

 

USXGMII core can be used to achieve  10G with external PHY. USXGMII Core is in compliance with the  NBASE-T Alliance. I believe the part datasheet will have details about the compliance of this. 

As per the linux drive, please refer:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842485/Linux+AXI+Ethernet+driver

 

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