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Newbie uuii9o
Registered: ‎12-24-2007

Maintenance read or write with rapidio switch Tsi568

I use Virtex-II Pro 2vp30 devices with the RapidIO IP core v3.1 to communicate with RapidIO switch Tundra Tsi568.
The data packets through Tsi568 between two FPGA endpoints have no problem, but errors occur (iresp_state[0:3] == 4'b0111) when I read and write the switch's CSR, using maintenance read or write operations.  (ireq_ftype[0:3] == 4'b1000, ireq_ttype == 4'b0000 or 4'b0001)
I want to know whether the RapidIO IP core can access the switch's CSR. (The Tsi568 declares it supports 4 bytes maintenance request only, and the IP core offers 64bit data width to user interface). Only that I can use FPGA as a host to configer the switch's LUT.
Thank you!
Merry christmas!
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