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egrigor
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Registered: ‎12-11-2007

Missing Unisim files for UltraScale+ Causes Questasim Errors when simulating with 1G/2.5G PCS/PMA or SGMII core

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I'm running Vivado 2019.1.3 and using Questasim-64 2019.2 as my Verilog simulator on a Win10-64 platform.  In Vivado, I have already compiled the full simulation libraries and use the generated modelsim.ini file in my project's folder to simulate my design which includes an instance of the IP Manager generated/customized version of 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE.  I see the following errors in Questasim:

# ** Error: C:\Xilinx\Vivado\2019.1\data\verilog\src\unisims\BITSLICE_CONTROL.v(629): Module 'SIP_BITSLICE_CONTROL_D1' is not defined.
# ** Error: C:\Xilinx\Vivado\2019.1\data\verilog\src\unisims\RX_BITSLICE.v(428): Module 'SIP_RX_BITSLICE_D1' is not defined.
# ** Error: C:\Xilinx\Vivado\2019.1\data\verilog\src\unisims\RX_BITSLICE.v(428): Module 'SIP_RX_BITSLICE_D1' is not defined.
# ** Error: C:\Xilinx\Vivado\2019.1\data\verilog\src\unisims\BITSLICE_CONTROL.v(629): Module 'SIP_BITSLICE_CONTROL_D1' is not defined.
# ** Error: C:\Xilinx\Vivado\2019.1\data\verilog\src\unisims\TX_BITSLICE.v(410): Module 'SIP_TX_BITSLICE_D1' is not defined. 

So the tool is not seeing definitions for these 3 modules:  SIP_BITSLICE_CONTROL_D1, SIP_RX_BITSLICE_D1 and SIP_TX_BITSLICE_D1

In modelsim.ini, the unisims and unisims_ver are mapped as follows:

unisim = C:/data/xilinx_sim_lib/unisim
unisims_ver = C:/data/xilinx_sim_lib/unisims_ver

but as can be seen from the error messages, Questa is looking for these under "C:\Xilinx\Vivado\2019.1\data\verilog\src\unisims\"

I looked in the "C:/data/xilinx_sim_lib/unisims_ver" directory to see why Questa is looking at  "C:\Xilinx\Vivado\2019.1\data\verilog\src\unisims\" for these files.  The best I can tell from ".cxl.verilog.unisim.unisim.nt64.rpt' file with contents shown below (not sure this is the relevant file), is that's what the Xilinx generated "Compile Simulation Libraries' process is creating this path reflector:

CxlResult:C:\data\xilinx_sim_lib/unisims_ver/.cxl.verilog.unisim.unisim.nt64.rpt =
ExecutionPlatform = nt64 ,
SourceLibrary = unisim ,
SourcePath = C:\Xilinx\Vivado\2019.1\data/verilog/src ,
Simulator = questasim ,
SimulatorVersion = 2019.2 ,
CompiledLibrary = unisims_ver ,
CompiledPath = C:\data\xilinx_sim_lib/unisims_ver ,
Timestamp = Mon May 11 04:50:20 2020 ,
Time = 1589172618 ,
Language = verilog ,
XilinxVersion = 2019.1.3 ,
LogFile = C:\data\xilinx_sim_lib/unisims_ver/.cxl.verilog.unisim.unisims_ver.nt64.log ,
NumOfErrors = 0 ,
NumOfWarnings = 0 ,

The questions I have are:

1. Why are those 3 files missing from the unisims or unisims_ver library compilations?

2.  Where do I find these files and how do I get the simulator to see these?

For reference, I'm enclosing the generated modelsim.ini file that was genrated during the Compile SImulation Libraries process.

Thank you in advance for your help.

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egrigor
Contributor
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Registered: ‎12-11-2007

I realized what the issue was after Googling 'SIP_BITSLICE_CONTROL_D1' and finding out that the cryptic 'SIP' in the name is the acronym used for "Secure IP".

So I added '-L secureip' switch to both my vopt and vsim commands to my Questa DO compile script.  This loads the secureip library, and it resolved the errors and now the whole design compiles.

My issue is now resolved.  Included these comments in case others encounter these errors during thier compilation. 

View solution in original post

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egrigor
Contributor
Contributor
555 Views
Registered: ‎12-11-2007

I realized what the issue was after Googling 'SIP_BITSLICE_CONTROL_D1' and finding out that the cryptic 'SIP' in the name is the acronym used for "Secure IP".

So I added '-L secureip' switch to both my vopt and vsim commands to my Questa DO compile script.  This loads the secureip library, and it resolved the errors and now the whole design compiles.

My issue is now resolved.  Included these comments in case others encounter these errors during thier compilation. 

View solution in original post

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