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Registered: ‎03-27-2017

Multi-Lane TX/RX w/ Chip2Chip & Aurora

I would like to TX/RX 256 bits of data between chips. This is a proposed architecture:

On the TX side:

The 256 data bits are split 128/128 to 2 seperate C2C instantiations and then recombined to a 256 bit word into a single Aurora 64/66b instantiation. 


The RX side would just be the reverse of the architecture above, reclaiming the whole 256 bit word on the other chip.

Each C2C has a single valid/ready pair for TX/RX - I'm thinking of just combining signaling pairs from both C2Cs with combinatorial logic.

Is this method doable? Is there a better way to transmit words >128 bits? Does the Aurora ensure multi-lane data is not skewed upon arrival? 

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1 Reply
Xilinx Employee
Xilinx Employee
Registered: ‎03-30-2016

Hello @bfung 

1. I don't think your proposed IP configuration is feasible.
    The reason is AXI CHIP2CHIP has FIFO inside the IP. If you instansiated two C2C IP, those two IPs will work independently. There is no guarantee that the C2C stream output into Aurora 64B66B TX input is aligned.

2. If the 256-bits data is not AXI protocol, why not using Aurora 64B/66B with 4 lanes instead ?
You will have 256bit AXI-stream I/F on Aurora IP.

Hope this helps.

Thanks & regards