05-26-2014 12:32 AM
A couple of months ago I had some issues to get my Ethernet data path working on the VC709 connectivity board. This was an initial design that only contained two sets of Tri-Mode Ethernet MAC core and Ethernet 1000BASE-X PCS/PMA or SGMII combos that were cross connected and logic for configuration purposes. With this design I was able to setup a SMGII link between the 1000base-x core and the SFP transceiver, the medium link between the SFP and the NIC of the test PC and transferring packets through this bare data path.
Using this design as starting point I extended the design by instantiated our IP core in the data path and added more IP cores from Xilinx to build our required system.
After placement and routing, the FPGA is utilized for 75% and it seems that the timing report does not report issues.
When I try to setup the Ethernet data path with this image, I’m not able to setup a SGMII-link between the 1000base-x core and the SFP transceiver . (SGMII-link is bit of Status register in the gig-eth-pcs-pma core.)
To keep the critical logic together, I created pblocks for the Tri-Mode Ethernet MAC core and Ethernet 1000BASE-X combos and place them as close as possible to the transceiver modules but without success.
Does anyone have experience with this or give me some suggestions to look at?
05-26-2014 01:36 AM
Check the debugging section of the below doc.
05-26-2014 05:27 AM
Thank you for your quick response.
I’m familiar with this debugging section since I struggled with getting the SMGII links active before while debugging the bare data path mentioned in my previous post.
Since the FPGA is much more utilized compared with the bare data path, I’m afraid I have to deal with timing issues. The timing report reports some unconstrained input/output ports and I know that the rxn/rxp and txn/txp signals are part them. I tried to find more information on the Xilinx website/forum and reference designs how to constrain these signals for the Virtex-7 VC706 board without any success.
Dou you have more information about how to constrain these signals? Any help is appreciated.