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Observer
Observer
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Registered: ‎07-07-2020

O-RAN IF IP Core: Error when trying to generate hardware description file (.xsa )

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Hey,

Recently I've been trying to generate the hardware description file (.xsa ) from the ORAN IF IP Core by using the tcl scripts available in the github repo, and I've been getting the following errors when running the Implementation (I'm targetting the ZCU102 board):

ERROR: [Common 17-70] Application Exception: Unable to get BIT file from implementation run. Please ensure implementation has been run all the way through Bitstream generation. Aborting write_hw_platform..

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To be clear, the procedure I took went as follows:

- Openned Vivado, and through the TCL console went to the downloaded github repository, more specifically the scripts folder;

- Afterwards I ran the following script to show me the available commands:

source ./xil_vivado_build.tcl 

 

which led me to build the project like this: 

::roe::bin::createIp_runIpiBuild "" om5 zcu102 true

 

- Once this was complete I ran the implementation:

::roe::bin::run_impl

 

which ran the synthesis without problems but resulted in the errors shown above.

Hope you could shine some light on this issue

Thanks.

 

 

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Xilinx Employee
Xilinx Employee
154 Views
Registered: ‎08-02-2007

@vessils 

For the new error message, it indicates that you don't have valid license for 10G/25G Ethernet IP. Please work with your FAE, and try to get a valid license

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Xilinx Employee
Xilinx Employee
311 Views
Registered: ‎08-02-2007

@vessils 

I will try the exact flow, and then let you know if I can reproduce the problem

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

@vessils 

When I tried source ./xil_vivado_build.tcl, nothing happened, only tcl command was printed in the tcl console.

please use command below, and see if it makes any difference

vivado -mode tcl -source ./xil_vivado_build.tcl -tclargs zcu102 -tclargs om5            -tclargs implNodateExit

 

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Observer
Observer
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Registered: ‎07-07-2020

Hey,

I did run that command the first time, but with no success. Now I tried again and found out the problem - the pathing wasn't correct, and so the vivado command wasn't being recognized (on Windows). Now it finnaly ran but still got the same error:

Starting Logic Optimization Task

Phase 1 Generate And Synthesize Debug Cores
INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub
ERROR: [Chipscope 16-302] Could not generate core for dbg_hub. Aborting IP Generation operaion. The current Vivado temporary directory path, 'C:/Users/francisco.serodio/Desktop/wireless-xorif-master/output/zcu102_om5_exs_2020_1/vivado/zcu102_om5_exs_2020_1.runs/impl_1/.Xil/Vivado-10816-it-rf1', is 151 characters. Errors on the host OS will occur when trying to insert logic for debug core 'dbg_hub' when temporary directory paths exceed 146 characters. Please move this Vivado project or the Vivado working directory to a shorter path; alternately consider using the OS subst command to map part of the path to a drive letter.


Phase 1 Generate And Synthesize Debug Cores | Checksum: ebb1d266

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 3262.316 ; gain = 0.633
INFO: [Common 17-83] Releasing license: Implementation
116 Infos, 52 Warnings, 0 Critical Warnings and 2 Errors encountered.
opt_design failed
ERROR: [Chipscope 16-338] Implementing debug Cores failed due to earlier errors
INFO: [Common 17-206] Exiting Vivado at Thu Aug 20 17:42:42 2020...
[Thu Aug 20 17:42:46 2020] impl_1 finished
WARNING: [Vivado 12-8222] Failed run(s) : 'impl_1'
wait_on_run: Time (s): cpu = 00:00:13 ; elapsed = 00:14:56 . Memory (MB): peak = 2692.203 ; gain = 0.000
INFO: [Vivado 12-4895] Creating Hardware Platform: C:/Users/francisco.serodio/Desktop/wireless-xorif-master/output/zcu102_om5_exs_2020_1/vivado/zcu102_om5_exs_2020_1.sdk/zcu102_om5_exs_2020_1.xsa ...
INFO: [Hsi 55-2053] elapsed time for repository (C:/Xilinx/Vivado/2020.1/data\embeddedsw) loading 0 seconds
Fall back to HDF output, placing in C:/Users/francisco.serodio/Desktop/wireless-xorif-master/output/zcu102_om5_exs_2020_1/vivado/zcu102_om5_exs_2020_1.sdk
ERROR: [Common 17-70] Application Exception: Unable to get BIT file from implementation run. Please ensure implementation has been run all the way through Bitstream generation. Aborting write_hw_platform..
Vivado%~

Hope you can help me with this issue - meanwhile I generated the .xsa manually through vivado with the example system, but, of course, would prefer to generate it with the provided tcl commands. Either way I'm having an issue building up the Petalinux project, which I already described here https://forums.xilinx.com/t5/Embedded-Linux/ORAN-IF-IP-Core-Example-System-failed-to-build-Petalinux-using/m-p/1138802#M44412 , and I hope you could help me with it.

Thanks for the help so far.

 

 

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Xilinx Employee
Xilinx Employee
248 Views
Registered: ‎08-02-2007

@vessils 

It's a known issue in windows, as the path is too long. 

In this case, you need to manually create a project on super short path, and then add Oran IP to block design, and then run block automation, generate bitstream, and then export hardware to xsa, to generate xsa file. 

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Observer
Observer
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Registered: ‎07-07-2020

A few minutes after I posted the previous response I noticed exacly that error message, and so I tried moving the directory to C, in order to achieve a shorter path name.

This time it bypassed the issue, but got another one: 

Command: write_bitstream -force design_1_wrapper.bit
Attempting to get a license for feature 'Implementation' and/or device 'xczu9eg'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu9eg'
INFO: [Common 17-83] Releasing license: Implementation
333 Infos, 54 Warnings, 0 Critical Warnings and 1 Errors encountered.
write_bitstream failed
ERROR: [Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted:
design_1_i/datapath/xxv_eth_subs/xxv_wrap/xxv_ethernet_0/inst/i_design_1_xxv_ethernet_0_0_top_0/i_design_1_xxv_ethernet_0_0_CORE (<encrypted cellview>)
If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation.
INFO: [Common 17-206] Exiting Vivado at Thu Aug 20 18:56:16 2020...
[Thu Aug 20 18:56:21 2020] impl_1 finished
WARNING: [Vivado 12-8222] Failed run(s) : 'impl_1'
wait_on_run: Time (s): cpu = 00:00:19 ; elapsed = 00:27:50 . Memory (MB): peak = 2687.285 ; gain = 0.000
INFO: [Vivado 12-4895] Creating Hardware Platform: C:/wireless-xorif-master/output/zcu102_om5_exs_2020_1/vivado/zcu102_om5_exs_2020_1.sdk/zcu102_om5_exs_2020_1.xsa ...
INFO: [Hsi 55-2053] elapsed time for repository (C:/Xilinx/Vivado/2020.1/data\embeddedsw) loading 0 seconds
Fall back to HDF output, placing in C:/wireless-xorif-master/output/zcu102_om5_exs_2020_1/vivado/zcu102_om5_exs_2020_1.sdk
ERROR: [Common 17-70] Application Exception: Unable to get BIT file from implementation run. Please ensure implementation has been run all the way through Bitstream generation. Aborting write_hw_platform..

If its not possible to proceed to generate through this flow, I'll do it manually, as I already did previously. 

Thanks for the help.

 

 

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Highlighted
Xilinx Employee
Xilinx Employee
155 Views
Registered: ‎08-02-2007

@vessils 

For the new error message, it indicates that you don't have valid license for 10G/25G Ethernet IP. Please work with your FAE, and try to get a valid license

View solution in original post