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Observer
Observer
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Registered: ‎07-07-2020

ORAN IF IP: Demonstrating with Example System (xorif-app)

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Hello, 

I'm trying to use the example system with the respective xorif-app to demonstrate the core, but with no success. I already have the system successfully implemented on 2x ZCU102 boards, connected through a ETH 10G link, while running the xorif-app on one of them as server and the other as client (connected through 10/100 ETH) and controlling both through UART on a LINUX host machine. As you can see in ran it with no problems:

root@zcu102_om5_exs:/usr/bin# xorif-app -n 192.168.0.55 -m

 __  _____  ____  ___ _____       _    ____  ____  
 \ \/ / _ \|  _ \|_ _|  ___|     / \  |  _ \|  _ \ 
  \  / | | | |_) || || |_ _____ / _ \ | |_) | |_) |
  /  \ |_| |  _ < | ||  _|_____/ ___ \|  __/|  __/ 
 /_/\_\___/|_| \_\___|_|      /_/   \_\_|   |_|    
�© Copyright 2020 ��– 2020 Xilinx, Inc. All rights reserved.

init   => status = 0

XORIF-APP Main Menu
===================
  1) Versions
  2) Capabilities
  3) Component carrier configuration
  4) Ethernet configuration
  5) Read/write registers and memory
  6) Read stats / counters
  7) Debug trace
  8) Reset FHI
100) Exit

Enter : 

The problem is I can't seem to see the core in action with the "Read stats/counters" option, even after I configured the core with a simple example configuration:

Enter : 10
get cc_config 0 => status = 0
num_rbs = 20
numerology = 0
extended_cp = false
iq_comp_meth_ul = 0
iq_comp_width_ul = 0
iq_comp_meth_dl = 0
iq_comp_width_dl = 0
bw_comp_meth = 1
bw_comp_width = 12
deskew = 160
advance_ul = 100
advance_dl = 100
num_ctrl_per_sym_ul = 64
num_ctrl_per_sym_dl = 64

XORIF-APP Component Carrier Configuration Menu
==============================================
  1) Set component carrier number (current = 0)
  2) Set number of RBs
  3) Set numerology
  4) Set time advance offsets
  5) Set uplink IQ compression
  6) Set downlink IQ compression
  7) Configure component carrier
  8) Enable component carrier
  9) Disable component carrier
 10) Get component carrier configuration
 11) Get component carrier allocation
 99) Back to previous menu
100) Exit

Enter : 11
get fhi_cc_alloc 0 => status = 0
enabled = true
num_rbs = 20
numerology = 0
ul_ctrl_sym_num = 4
ul_ctrl_offset = 0
ul_ctrl_unroll_offset = 0
ul_ctrl_base_offset = 0
dl_ctrl_sym_num = 4
dl_ctrl_offset = 0
dl_ctrl_unroll_offset = 0
dl_data_sym_num = 4
dl_data_sym_start = 0
dl_data_buff_size = 130
dl_data_buff_start = 0

When I try to read the FHI registers related to the packet count, I only see the overall count increasing very slowly, but none of them are classified into control or user data packet:

XORIF-APP Read Stats/Counters Menu
==================================
  1) Read FHI stats
 99) Back to previous menu
100) Exit

Enter : 1
get fhi_stats => status = 0
total_rx_good_pkt_cnt = 116
total_rx_bad_pkt_cnt = 0
total_rx_bad_fcs_cnt = 0
user_data_rx_packets_cnt = 0
user_data_rx_good_pkt_cnt = 0
user_data_rx_bad_pkt_cnt = 0
user_data_rx_bad_fcs_cnt = 0
user_ctrl_rx_packets_cnt = 0
user_ctrl_rx_good_pkt_cnt = 0
user_ctrl_rx_bad_pkt_cnt = 0
user_ctrl_rx_bad_fcs_cnt = 0
user_data_rx_pkts_rate = 0
user_ctrl_rx_pkts_rate = 0

I tried running the startup script and noticed an error while trying to run a certain command: "Setting timestamped mode using hwstamp_ctl... /usr/bin/xroe-config-XXV-ptp.sh: line 30: hwstamp_ctl: command not found"

User startup script /usr/bin/runXorif.bash exists. Executing,
**********************************************************************
** /usr/bin/runXorif.bash
** Xilinx ORAN Radio I/F demonstration platform application initscr **
**********************************************************************
** Ethernet Interfaces 10G = eth0, 10/100 = eth1
** Supported antennas: 0x00000000
Update the AXI4 timeout so we know this has been executed
Switch the LED mode
Bring the 10/100 link down->up
[ 3709.737336] macb ff0e0000.ethernet: gem-ptp-timer ptp clock unregister.
[ 3709.749792] macb ff0e0000.ethernet eth1: link up (1000/Full)
[ 3709.755586] pps pps1: new PPS source ptp1
[ 3709.759616] macb ff0e0000.ethernet: gem-ptp-timer ptp clock registered.
Unit is master assign IP address 9 on eth0
Setting up the XXV Ethernet link eth0 IP= 192.168.99.9
RTNETLINK answers: File exists
Setting timestamped mode using hwstamp_ctl...
/usr/bin/xroe-config-XXV-ptp.sh: line 30: hwstamp_ctl: command not found
1: lo: <LOOPBACK,UP,LOWER_UP> mtu 65536 qdisc noqueue state UNKNOWN group0
    link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00
    inet 127.0.0.1/8 scope host lo
       valid_lft forever preferred_lft forever
    inet6 ::1/128 scope host 
       valid_lft forever preferred_lft forever
2: eth0: <BROADCAST,UP,LOWER_UP> mtu 1500 qdisc pfifo_fast state UNKNOWN 0
    link/ether 8e:95:1f:16:39:66 brd ff:ff:ff:ff:ff:ff
    inet 192.168.99.0/24 brd 192.168.99.255 scope global eth0
       valid_lft forever preferred_lft forever
    inet 192.168.99.9/24 scope global secondary eth0
       valid_lft forever preferred_lft forever
    inet6 fe80::8c95:1fff:fe16:3966/64 scope link 
       valid_lft forever preferred_lft forever
3: sit0@NONE: <NOARP> mtu 1480 qdisc noop state DOWN group default qlen 10
    link/sit 0.0.0.0 brd 0.0.0.0
4: can0: <NOARP,ECHO> mtu 16 qdisc noop state DOWN group default qlen 10
    link/can 
5: eth1: <NO-CARRIER,BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq s0
    link/ether 00:0a:35:04:8d:ee brd ff:ff:ff:ff:ff:ff
    inet 192.168.0.55/24 brd 192.168.0.255 scope global eth1
       valid_lft forever preferred_lft forever
    inet 192.168.10.100/24 scope global eth1
       valid_lft forever preferred_lft forever
    inet 192.168.99.10/24 scope global eth1
       valid_lft forever preferred_lft forever
...done!
RTNETLINK answers: File exists
[ 3710.747557] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready
Bring the 10G link down->up one last time to flush system

I'm hoping someone can help with this issue - What am I doing wrong? What can I do to show the example system in action? 

Thanks in advance.

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Xilinx Employee
Xilinx Employee
221 Views
Registered: ‎08-02-2007

@vessils 

If you use open IP example design flow, you should be able to see the generated pcap file in the sim folder. This pcap should contain very basic pattern. For the comprehensive one, you need to use a proper O-DU. It's outside the scope of O-RAN IP, which provides O-RU function only. 

For the exact flow on how to generate IP example design simulation, I've documented in https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/A-tale-of-two-RoE-Radio-Over-Ethernet-demos-Simulation/ba-p/1140341

Even it's for RoE, it should be very similar in O-RAN IP. 

View solution in original post

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Xilinx Employee
Xilinx Employee
316 Views
Registered: ‎08-02-2007

@vessils 

The Example System intends to demonstrate the behavior in client mode. If you connect the real O-DU to ZCU102 board, you should be able to see the proper C-Plane and U-Plane message.

We plan to release single board demo. The test blocks are included in the example design. I will need to double check if it's available or not, and then get back to you

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Observer
Observer
304 Views
Registered: ‎07-07-2020

@xud 

Hmm it makes sense - I was struggling to understand how the example system would emulate a O-DU, but at the same time, I couldn't figure out how implementing the example system by itself would demonstrate the core in action - thats why I implemented the example system on both boards.

So with the O-DU connected to the example system implemented in a ZCU102 board, the 'xorif-app server' would run on the ZCU102 while the 'xorif-app client ' on a Linux host machine, correct (monitoring and configuring this way the core) ?  

I wanted to use the example system as a testbench, and having something that would emulate a O-DU on a ZCU102 that I could connect to another ZCU102 with the example system on it would be perfect.

How does the single board demo intend to demonstrate the system? By emulating the O-DU in the same design (with no physical 10G ETH connection) i.e. an "internal loopback"? 

Thanks for the awnser - looking foward to the single board demo availability, since I don't have a O-DU available to use in a testbench.

 

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Xilinx Employee
Xilinx Employee
222 Views
Registered: ‎08-02-2007

@vessils 

If you use open IP example design flow, you should be able to see the generated pcap file in the sim folder. This pcap should contain very basic pattern. For the comprehensive one, you need to use a proper O-DU. It's outside the scope of O-RAN IP, which provides O-RU function only. 

For the exact flow on how to generate IP example design simulation, I've documented in https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/A-tale-of-two-RoE-Radio-Over-Ethernet-demos-Simulation/ba-p/1140341

Even it's for RoE, it should be very similar in O-RAN IP. 

View solution in original post

Highlighted
Observer
Observer
208 Views
Registered: ‎07-07-2020

Hello @xud ,

Thanks for the answer,  I've been able to get access to a O-DU, but haven't arrived yet - meanwhile I will try out the pcap generation and the example's design simulation.

 

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