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wierzmar
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Registered: ‎04-08-2021

ORAN IP configuration: eAxC mapping

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Hi,

I am trying to understand ORAN IP configuration from SW perspective.

According to O-RAN.WG4.CUS.0-v04.00 specification it shall be possible to assign particular eAxC ID to RU endpoint. How is it accomplished by ORAN IP? Is it possible to configure it by SW?

Thank you.

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xud
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

@wierzmar 

I want to check if my last reply clarified the issue, do you have any more questions related to this?

View solution in original post

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xud
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

@wierzmar 

Yes, it has been describe in pg21 of PG370. xorif_set_fhi_eaxc_id and xorif_set_ru_ports can be used to configure the way to detect eAxC ID 

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wierzmar
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Registered: ‎04-08-2021

Thanks. As far as I understand those functions are for configuring bits distribution between different fields like DU_port_id, BandSector, CC_id, RU_port_ID.

And, what is missing for me is mapping from eAxCid to RU endpoint (DL datapath). But, it looks like the ORAN IF IP is not the one to configure this mapping (?). And, there probably should be some way (another FPGA IP ?) to tell which eAxC should reach which endpoint.

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xud
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

@wierzmar 

You are correct,  xorif_set_fhi_eaxc_id  is for bit distribution 

For example, if you have eAxC ID as below : 

xud_0-1618226856315.jpeg

To configure ORAN IP, you need to use following commands to match the settings from DU : 

xud_1-1618226929560.jpeg

Then you can use xorif_set_ru_ports to decide the final ID. It depends on the Stream Identifying mask and other mask bits.

For example, if you use xorif_set_ru_ports (8, 5, 0xC0, 0, 0x80, 0x40), the value 0xC0 needs to be ANDed with other masked bits.

The PRACH mask is 0x80, so the ID is 0xC0 AND 0x80 = 1000 0000 (Binary).[7:6] 10(binary)=2 (DEC), which is the final RU_Port_ID

If you set PRACH mask to 0xC0,and then the ANDed value is 1100 0000, [7:6] is 11(binary)=3 (DEC), so the final RU_Port_ID is 3. 

 

 

xud
Xilinx Employee
Xilinx Employee
704 Views
Registered: ‎08-02-2007

@wierzmar 

I want to check if my last reply clarified the issue, do you have any more questions related to this?

View solution in original post

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