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joab1
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Registered: ‎09-01-2020

On-board Ethernet between two Zynq Ultrascale

Hi. Is it possible to use the IP 1G/2.5G Ethernet PCS/PMA or SGMII (16.1) to establish a ethernet connection between two zynq ultrascales on the same board without external phys? I am using Pelalinux and it would be perfect if there is a way to emulate a ethernet phy in PL so the communication between the zynq ultrascales look like a regular ethernet link from the Linux OS.

 

Thank you for taking your time.

 

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shabbirk
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Registered: ‎12-04-2016

Hi @joab1 

If you are using 1000base-x/sgmii SFP's at both the board sides for the testing then it's possible. We do have XAPP1305 for PL ethernet 1000base-x/sgmii here for your reference:

https://github.com/Xilinx-Wiki-Projects/ZCU102-Ethernet/tree/main/2019.2/pl_eth_1g

 

Regards

Shabbir

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joab1
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Registered: ‎09-01-2020

Thank you. I find it a little unclear how to implement this in my vivado design(s). Is there any vivado example project available that can be used as refecrence?

Best regards

Johan

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dpaul24
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Registered: ‎08-07-2014

@joab1 ,

This is how communication at the MAC data link layer takes place b/w two eth sub-systems:

 mac-back_end <--> Eth MAC <--> PHY <-----wired/wireless connection-------> PHY <--> Eth MAC <-->  mac-back_end

Is it possible to use the IP 1G/2.5G Ethernet PCS/PMA or SGMII (16.1) to establish a ethernet connection between two zynq ultrascales on the same board without external phys?

Now in your case, the PHYs are missing (you do not have to emulate the PHY). So for your design the connectivity becomes....

mac-back_end <--> Eth MAC <- mac-front_end to mac-front_end-> Eth MAC <-->  mac-back_end

This is basically the concept. The mac-front_end to mac-front_end protocol can be anything SGMII/RMII/RGMII/GMII, whatever suits yours design. You just tie the rx lines to the tx lines and vice-versa. Take care about the clocking. That's it.

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bitjockey
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Registered: ‎03-21-2011

Technically I suppose the PCS_PMA that the RocketIO/SelectIO silicon is being configured as is still "PHY" under the hood, just without the final electrical-to-optical conversion of the usual fiber, and staying electrical instead.   You are right that any of the *MIIs will work.  SGMII and the PCS/PMA will require RocketIO (whoops, I was thinking 10G and/or 7-series products that don't do 1G SelectIO) but will have the benefit of being a pair of LVDS pairs which is a differential routed pair (x2) on the circuit board.  Any of the other *RMIIs are parallel single-ended, (though still source-synchronous chanels) which will make the circuit board a little bit more complex/congested, but can use regular GPIO and not the RocketIO silicon inside the chip.  It's a tradeoff.

Note that for SGMII/SerDes connection will likely need DC blocking capacitors in series on the diff pair for the LVDS signaling (not a big deal, but don't forget them).  It's always way harder to add them after the board is manufactured :-P.

Update https://www.xilinx.com/support/documentation/ip_documentation/gig_ethernet_pcs_pma/v16_2/pg047-gig-eth-pcs-pma.pdf seems to indicate that SelectIO in even the 7 series can be made to work in SGMII mode, just not 1000BASE-X mode, if the speed grade is right.  This confuses me because electrically both are the same 8B10B 1.25Gbps physical signaling with slight data differences only--timing and signaling speed/levels are the same.

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