03-05-2019 12:11 AM
i am trying to achieve optical link between two Kintex FPGA board. In the xilinx forum, xapp1211-aurora8b/10b-simplex-kc705 document is used for this purpose but i examined this document and saw that example design was provided serial data link using sma connector. But, we provide optical link using sfp connector and how should i follow a path for my aim? and would it be correct to use this example design? Secondly, the example design used 156,25 MHz reference clock and provided this clock from external clock generator. Can Kintex FPGA board not provide this clock rate?
03-06-2019 10:29 AM
Hi @34498453482 ,
If your requirement is to implement a Simplex link, you can start with the XAPP. Since you are using an optical link, you might need to enable LPM equalization with the IP. You can do this by enabling the "Additional Transceiver Control and Status Ports" option with the IP and connecting gt<lane>_rxlpmen_in to 1'b1.
With KC705, 156.25MHz frequency clock is not available to be connected with GT's. You can use the SGMII clock (125MHz) available on the board to drive your design if your target data rate can be supported by this clock frequency. To do this change, you will need to change the refclk location with the design to connect to SGMII clock.
03-07-2019 03:34 AM
Thanks for your answer. I have some question about this issue. Firstly, sgmii clock frequency can support my data rate but i don't know that how to use this clock in my design. I think it is enough to change constraint file for refclk, but i wasn't sure. Secondly, my FPGA board has changed to virtex7, so do i need to make any changes to the example design?