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Explorer
Explorer
2,316 Views
Registered: ‎12-18-2014

PICXO-IP ERROR_O Output very high

Hi,

i am using the picxo-ip where the REF-Input is a hsync(31,51 KHz) and the TXOUTCLK/TXUSRCLK from the Transceiver is the Pixel Clock(33,27 MHz). For the R-Divider for hsync i set to 1(decimal) and for V-Divider 1056(decimal). What might be the reason for the -39136(signed) Error on the output of the phase frequency detector. The Video Signals are coming from graphics source where HSYNC and Pixel Clock are in phase(verified on scope). 

response of picxo DVI_CLOCK_33_27_MHz.JPG
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Xilinx Employee
Xilinx Employee
2,059 Views
Registered: ‎01-22-2008

Re: PICXO-IP ERROR_O Output very high

Hi Sevenclock,

 

I think the R and V values are incorrect: the R and V divider have a +2 build in, so you are actually setting R to 3 and V to 1058.

 

Thanks

Vincent

 

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