10-30-2016 04:40 PM
I like to design my own PCS to interface with the PMA block. I understand that the PMA block is a hard logic IP. Like to know if you have specific materials for PMA block design so I could design my PCS to fit the requirements of PMA?
I find that the 10G PCS/PMA IP is free however, the RTL is encrypted. Any lead that I could purchase the source code as an alternative? Like to do front end optimization and customization to the IP architecture.
10-30-2016 08:36 PM
I also like to write my own PCS (and MAC) layers.
The "PMA" reference you want is the transceiver user guide and the FPGA family datasheet as well as the wealth of answer records and example designs and forum posts.
Unfortunately you didn't say which parts you were interested in.
Your design will need to target a particular family of parts, as the transceiver details will vary from family to family.
10-31-2016 05:22 PM
I assume to target the Ultrascale device to begin with. Anyhow, it seems the wealth of information is here and there. Any particular useful ones? I recon the PCS logic that needs more attention is the gearbox and 64/66b encoding logic. What are your thoughts?
11-01-2016 09:55 PM
There is a degree of 10GbE support in hardware. You could use the hard gearbox (which seems to do block detection as well). Pretty much everything else must be done in your design.
One way to proceed would be to treat the GTH / GTY as a dumb serdes. At least that way you will control every aspect of the design. It will be as portable as you can make it (as it doesn't rely on any unique features of a particular FPGA). It's also easy to simulate and test - you won't need to use any vendor libraries. Also, if there's a bug, you know you can fix it.
There will be a slight area and power benefit to using the supplied gearbox though. Possibly a latency benefit as well.
My experience has been that (if you're not using a wizard) using the hard cores does not necessarily result in a quicker project.