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georgios.rizeakos
Adventurer
Adventurer
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Registered: ‎10-03-2019

PMA implementation 100G CMAC

It is a bit confusing how PMA is implemented in 100G CMAC. As far as I understand the main point for PMA is to get the PCS lanes and provide a bit stream out of them down to PMD.

That picture bellow from pg203 illustrates the transition from PCS to PMD. If that is the case does it display the general functionality of PMA?

The standard specifies as PCS lanes the 20 VLs made of 66 bit blocks at a time. Which it is expected to be but muxed and broken down to bit streams that are fed to the PMD. Yet in the picture it seems like the 16 bit lanes are muxed and passed directly to the PMD?

Furthermore, it is expected CAUI-4 to be “physical instantiation of the connection between 2 adjacent PMAs”. From the picture and information in pg203 seems like the output of the muxes goes to GT-Serdes (I cant see the PMA layering).

confusion-PCStoPMD.JPG

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georgios.rizeakos
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Registered: ‎10-03-2019

Could someone please help?

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guozhenp
Xilinx Employee
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Registered: ‎05-01-2013

CAUI-4 is 25G x4

There're 20 VLs. So every 5VLs goes to 1 physical lane (GT)

I think the picture shows 1 of them

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georgios.rizeakos
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Registered: ‎10-03-2019

Thank you very much for your reply,

So I guess that that answers my question "does it display the general functionality of PMA?" (meaning is that how PMA is implemented in CMAC?)

 

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aforencich
Explorer
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Registered: ‎08-14-2013

The CMAC has internal 16:66 gearboxes on each of the virtual lanes, so each lane can either generate or accept 16 bits on each clock cycle.  It's done this way because all of the numbers work out nicely - 5 bit-muxed VLs per serdes means you really want the serdes data width to be a multiple of 5 so you can do a static demux, so they use 80 bits which is 5*16.  Then each VL has to do block lock independently, which means you need 20 different places where you can bit slip, which means 20 16:66 gearboxes.  And the clock frequency with 80 bit serdes interfaces is 100G * 66/64 / (4*80) = 322.265625 MHz, which is not crazy high. 

guozhenp
Xilinx Employee
Xilinx Employee
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Registered: ‎05-01-2013

Yes, it answers.

If you have any more question about it, please feel free to let us know.

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