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n.horvat
Contributor
Contributor
768 Views
Registered: ‎02-19-2018

PS GEM - External FIFO Interface - RX

Hi,

I'm interested in using of PS "Gigabit Ethernet MAC" (GEM) controller with option "External FIFO Interface" enabled.
I need to send some data from PL to ethernet interface. With "AR# 69490" and "UG1085" process of sendind data from PL to PS GEM is well documented.

My question is related to Rx packets. If I understand correctly, on packet receive, PS GEM controller outputs rx packet to "External FIFO Interface".
Would those Rx packets also be available on CPU side (LWIP)?
In my design I don't want to process Rx packets in PL but I would like to process them with CPU (through LWIP).
So PL should send data and CPU should process rx packets.

Thank you.

 

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5 Replies
n.horvat
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Contributor
703 Views
Registered: ‎02-19-2018

Anyone?

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nishak
Moderator
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680 Views
Registered: ‎03-10-2020

Hi @n.horvat,

There is no driver support for using an External FIFO interface.
So, You won't be able to process RX packets with PS through LWIP. 

There is support for PS-GEM + 1000BASE-X PCS/PMA and PS-GEM + GMII2RGMII.

Could you provide more information about why do you want the mentioned solution?

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n.horvat
Contributor
Contributor
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Registered: ‎02-19-2018

I'm generating/collecting some data in PL and PL then generates axi-stream from this data.
Then this axi-stream from PL will be converted to "GEM - TX FIFO packet stream".
RX packets that are coming into PS - GEM need to be processed in PS and not in PL.

Reason why i whant to use PS - GEM in EMIO configuration instead for example AXI-EthernetSubsystem
is that PS-GEM supports IEEE 1588 timestamping (Precission Time Protocol) which I need for my project.

To avoid using PS GEM external fifo interface and use only GMII and MDIO through EMIO, I can transfer this
data from PL into DDR, read it with CPU and then transfer it via LWIP to the PS-GEM. BUT I would like to avoid
this solution and perfom "direct" transfer from PL to PS-GEM.

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nishak
Moderator
Moderator
646 Views
Registered: ‎03-10-2020

@n.horvat 

1. IEEE 1588 support is available in the AXI Ethernet subsystem, and

2. You can still process the packets received in the PS with PS-DMA in PS-PL design instead of opting for external FIFO interface.

Could you try the same?

Please provide block diagram of your design for more questions. Thanks.

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n.horvat
Contributor
Contributor
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Registered: ‎02-19-2018

1. "IEEE 1588 support is available in the AXI Ethernet subsystem.."
Only for 1000BASE-X or SGMII eth phy's. I'm using RGMII eth phy.

2. "You can still process the packets received in the PS with PS-DMA in..."
Lets sum up:
a) PS-GEM GMII through EMIO TO PL (then in PL - GMII to RGMII IP core)
b) PS-GEM MDIO through EMIO TO PL
c) PS-GEM Process RX packets with PS-DMA
d) TX Packets generated in PL - How to transfer them to PS-GEM? (Except my proposed way in a previous post)
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