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Visitor wanquantilkk
Visitor
289 Views
Registered: ‎10-08-2018

[Place 30-140] Unroutable Placement! A GTXE_COMMON / GTXE_CHANNEL clock component pair is not placed in a routable site pair.

Hi,

I met some troubles when I use 1g/2.5g subsystem on vc707.  I guess the problem is caused by the mgt_clk. Does anyone have an idea?

[Place 30-140] Unroutable Placement! A GTXE_COMMON / GTXE_CHANNEL clock component pair is not placed in a routable site pair. The GTXE_COMMON component can use the dedicated path between the GTXE_COMMON and the GTXE_CHANNEL if both are placed in the same clock region. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.

         < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets design_1_i/axi_ethernet_0/inst/pcs_pma/inst/core_gt_common_i/gt0_qplloutclk_out] >

 

         design_1_i/axi_ethernet_0/inst/pcs_pma/inst/core_gt_common_i/gtxe2_common_i (GTXE2_COMMON.QPLLOUTCLK) is provisionally placed by clockplacer on GTXE2_COMMON_X1Y1

          design_1_i/axi_ethernet_0/inst/pcs_pma/inst/pcs_pma_block_i/transceiver_inst/gtwizard_inst/inst/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i (GTXE2_CHANNEL.QPLLCLK) is locked to GTXE2_CHANNEL_X1Y1

 

         The above error could possibly be related to other connected instances. Following is a list of

         all the related clock rules and their respective instances.

 

         Clock Rule: rule_bufds_bufg

         Status: PASS

         Rule Description: A BUFDS driving a BUFG must be placed on the same half side (top/bottom) of the device

          design_1_i/axi_ethernet_0/inst/pcs_pma/inst/core_clocking_i/ibufds_gtrefclk (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X1Y0

          design_1_i/axi_ethernet_0/inst/pcs_pma/inst/core_clocking_i/bufg_gtrefclk (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y2

 

         Clock Rule: rule_bufds_gtxchannel_intelligent_pin

         Status: PASS

         Rule Description: A BUFDS driving a GTXChannel must both be placed in the same or adjacent clock region

         (top/bottom)

          design_1_i/axi_ethernet_0/inst/pcs_pma/inst/core_clocking_i/ibufds_gtrefclk (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X1Y0

          design_1_i/axi_ethernet_0/inst/pcs_pma/inst/pcs_pma_block_i/transceiver_inst/gtwizard_inst/inst/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i (GTXE2_CHANNEL.GTREFCLK0) is locked to GTXE2_CHANNEL_X1Y1

 

         Clock Rule: rule_bufds_gtxcommon_intelligent_pin

         Status: PASS

         Rule Description: A BUFDS driving a GTXCommon must both be placed in the same or adjacent clock region

         (top/bottom)

          design_1_i/axi_ethernet_0/inst/pcs_pma/inst/core_clocking_i/ibufds_gtrefclk (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X1Y0

          design_1_i/axi_ethernet_0/inst/pcs_pma/inst/core_gt_common_i/gtxe2_common_i (GTXE2_COMMON.GTREFCLK0) is provisionally placed by clockplacer on GTXE2_COMMON_X1Y1

 

         Clock Rule: rule_gt_bufg

         Status: PASS

         Rule Description: A GT driving a BUFG must be placed on the same half side (top/bottom) of the device

          design_1_i/axi_ethernet_0/inst/pcs_pma/inst/pcs_pma_block_i/transceiver_inst/gtwizard_inst/inst/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i (GTXE2_CHANNEL.RXOUTCLK) is locked to GTXE2_CHANNEL_X1Y1

          and design_1_i/axi_ethernet_0/inst/pcs_pma/inst/core_clocking_i/rxrecclkbufg (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y3

 

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Moderator
Moderator
205 Views
Registered: ‎11-09-2017

Re: [Place 30-140] Unroutable Placement! A GTXE_COMMON / GTXE_CHANNEL clock component pair is not placed in a routable site pair.

Hi @wanquantilkk

The error clarifies that GTXE_COMMON and its associated GTXE_CHANNEL are not placed in same clock region.Can you cross-verify constraints and make sure to follow this rule?

Make sure your reference clock is from one of the following.

GTREFCLK0 or GTREFCLK1 of same quad.

Quads above, GTSOUTHREFCLK0 or GTSOUTHREFCLK1.

Quads below, GTNORTHREFCLK0 or GTNORTHREFCLK1.

Regards
Pratap

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