UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor vagrawal2
Visitor
273 Views
Registered: ‎02-26-2018

[Place 30-510] Unroutable Placement

I have 2 separate Aurora cores I'd like to instantiate, each containing 4 lanes and sharing one refclk.  The "master" core has 'shared logic in the core' and the "slave" core has 'Include shared logic in the example design'. I hooked it up exaclty as in Figure 3-17 in pg074, but I get the following placement error:

[Place 30-510] Unroutable Placement! A GTHE_COMMON / GTHE_CHANNEL clock component pair is not placed in a routable site pair. The GTHE_COMMON component can use the dedicated path between the GTHE_COMMON and the GTHE_CHANNEL if both are placed in the same clock region.

It might be that each IP core is trying to share a single GTHE_COMMON, which I think is not allowed.

Should both IP cores be configured for 'shared logic in the core', and if so, how should I hook up the refclk?  In what case are you supposed to follow Figure 3-17 of the Aurora User's Guide?

Thanks.

 

 

0 Kudos
1 Reply
Teacher xilinxacct
Teacher
202 Views
Registered: ‎10-23-2018

Re: [Place 30-510] Unroutable Placement

@vagrawal2 

Do any of these solutions give you any insight?

https://forums.xilinx.com/t5/7-Series-FPGAs/Unroutable-Placement/m-p/417875#M3587
https://forums.xilinx.com/t5/7-Series-FPGAs/Place-30-139-Unroutable-Placement-PicoZed-7030-SOM/m-p/713541#M18001
https://forums.xilinx.com/t5/7-Series-FPGAs/Multiple-clock-gating-Unroutable-Placement-Errors/m-p/696302#M16547
https://forums.xilinx.com/t5/Embedded-Development-Tools/Unroutable-Placement/m-p/48301#M10732
https://forums.xilinx.com/t5/Implementation/Place-30-510-Unroutable-Placement/m-p/810325#M19455
https://forums.xilinx.com/t5/Implementation/ViRTEX7-How-to-resolve-quot-Place-30-136-Unroutable-Placement/m-p/729109#M16426
https://forums.xilinx.com/t5/Implementation/Error-Place-30-124-Unroutable-Placement/m-p/688125#M14964
https://forums.xilinx.com/t5/Implementation/Place-30-140-Unroutable-placement-A-GTXE-COMMON-GTXE-CHANNEL/m-p/671542#M14228
https://forums.xilinx.com/t5/Implementation/GT-BUFGCTRL-Unroutable-Placement/m-p/264146#M5311
https://forums.xilinx.com/t5/Implementation/ERROR-Place-1158-ERROR-Place-1160-Unroutable-Placement/m-p/317017#M6137
https://forums.xilinx.com/t5/Networking-and-Connectivity/Unroutable-Placement/m-p/474076#M6082
https://forums.xilinx.com/t5/Networking-and-Connectivity/Unroutable-placement/m-p/449032#M5746
https://forums.xilinx.com/t5/Serial-Transceivers/Place-30-140-Unroutable-Placement-A-GTXE-COMMON-GTXE-CHANNEL/m-p/735730#M1858
https://forums.xilinx.com/t5/Welcome-Join/Place-30-140-Unroutable-Placement-A-GTXE-COMMON-GTXE-CHANNEL/m-p/696363#M35917

Hope that helps

If so, please mark as solution accepted. Kudos also welcomed. :-)

0 Kudos