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tpdrjkt
Newbie
Newbie
580 Views
Registered: ‎04-29-2019

Placement error with multiple Aurora 64b/66b cores

I have a design in a Virtex 7 (xc7v2000tfhg1761) device that contains the following elements:

  1. Gen 2 x8 PCIe in SLR1
  2. DDR3 controller with I/O in SLR0
  3. Eight x1 Aurora 64b/66b transceivers using GTs in SLR0
  4. Six x1 Aurora 64b/66b transceivers using GTs in SLR2
  5. Two Microblazes, one to manage SLR0 Auroras and one to manage the SLR2 Auroras.
  6. Misc. AXI interconnects and 14 DMA controllers for the Aurora cores.

All the Aurora cores are configured for shared-logic in the example design.

When placing the design, I get the following error related to an Aurora transceiver in SLR2:

[Over-Constrained 1] tx_quad[0].tx_ch[0].u_sensor_fiber_tx/u_aurora_64b66b_x1_slr_2/inst/aurora_64b66b_x1_slr_2_wrapper_i/aurora_64b66b_x1_slr_2_multi_gt_i/aurora_64b66b_x1_slr_2_gtx_inst/gtxe2_i constrained such that no valid location exists on the device.

Last constraint applied is of type Tool:ClockSegment

 

The only constraint applied to the Aurora is pin location for the GT.

#-------------------------------------
# Aurora placement
#-------------------------------------
## BANK 117
set_property PACKAGE_PIN N2 [get_ports {aurora_tx_txp[0]}]
set_property PACKAGE_PIN P8 [get_ports {aurora_tx_rxp[0]}]

set_property PACKAGE_PIN M4 [get_ports {aurora_tx_txp[1]}]
set_property PACKAGE_PIN N6 [get_ports {aurora_tx_rxp[1]}]

set_property PACKAGE_PIN L2 [get_ports {aurora_tx_txp[2]}]
set_property PACKAGE_PIN L6 [get_ports {aurora_tx_rxp[2]}]

set_property PACKAGE_PIN K4 [get_ports {aurora_tx_txp[3]}]
set_property PACKAGE_PIN J6 [get_ports {aurora_tx_rxp[3]}]

set_property PACKAGE_PIN K8 [get_ports {aurora_tx_refclk_p[0]}]
set_property PACKAGE_PIN K7 [get_ports {aurora_tx_refclk_n[0]}]


###############################################################################
## BANK 118
set_property PACKAGE_PIN J2 [get_ports {aurora_tx_txp[4]}]
set_property PACKAGE_PIN H8 [get_ports {aurora_tx_rxp[4]}]

set_property PACKAGE_PIN H4 [get_ports {aurora_tx_txp[5]}]
set_property PACKAGE_PIN G6 [get_ports {aurora_tx_rxp[5]}]

set_property PACKAGE_PIN E10 [get_ports {aurora_tx_refclk_p[1]}]
set_property PACKAGE_PIN E9 [get_ports {aurora_tx_refclk_n[1]}]

I generated and xdc file using write_xdc to determine if any other physical constraints are applied to the Aurora cores, but there are none.

If I reduce the Aurora transceiver count to 4 in SLR0 (i.e. one quad) and 4 in SLR2 (one quad), then the design places without error.

I’ve tried creating PBlocks for the Auroras in SLR2 but get the same error. I’ve tried a placement constraint on the gtxe2 cells, instead of package pin constraints, but get the same error.

set_property LOC GTXE2_CHANNEL_X0Y24 [get_cells  tx_quad[0].tx_ch[0].u_sensor_fiber_tx/u_aurora_64b66b_x1_slr_2/inst/aurora_64b66b_x1_slr_2_wrapper_i/aurora_64b66b_x1_slr_2_multi_gt_i/aurora_64b66b_x1_slr_2_gtx_inst/gtxe2_i]

set_property LOC GTXE2_CHANNEL_X0Y25 [get_cells  tx_quad[0].tx_ch[1].u_sensor_fiber_tx/u_aurora_64b66b_x1_slr_2/inst/aurora_64b66b_x1_slr_2_wrapper_i/aurora_64b66b_x1_slr_2_multi_gt_i/aurora_64b66b_x1_slr_2_gtx_inst/gtxe2_i]

set_property LOC GTXE2_CHANNEL_X0Y26 [get_cells  tx_quad[0].tx_ch[2].u_sensor_fiber_tx/u_aurora_64b66b_x1_slr_2/inst/aurora_64b66b_x1_slr_2_wrapper_i/aurora_64b66b_x1_slr_2_multi_gt_i/aurora_64b66b_x1_slr_2_gtx_inst/gtxe2_i]

set_property LOC GTXE2_CHANNEL_X0Y27 [get_cells  tx_quad[0].tx_ch[3].u_sensor_fiber_tx/u_aurora_64b66b_x1_slr_2/inst/aurora_64b66b_x1_slr_2_wrapper_i/aurora_64b66b_x1_slr_2_multi_gt_i/aurora_64b66b_x1_slr_2_gtx_inst/gtxe2_i]

set_property LOC GTXE2_CHANNEL_X0Y28 [get_cells  tx_quad[1].tx_ch[0].u_sensor_fiber_tx/u_aurora_64b66b_x1_slr_2/inst/aurora_64b66b_x1_slr_2_wrapper_i/aurora_64b66b_x1_slr_2_multi_gt_i/aurora_64b66b_x1_slr_2_gtx_inst/gtxe2_i]

set_property LOC GTXE2_CHANNEL_X0Y29 [get_cells  tx_quad[1].tx_ch[1].u_sensor_fiber_tx/u_aurora_64b66b_x1_slr_2/inst/aurora_64b66b_x1_slr_2_wrapper_i/aurora_64b66b_x1_slr_2_multi_gt_i/aurora_64b66b_x1_slr_2_gtx_inst/gtxe2_i]

 

I’ve also tried several of the Vivado synthesis and implementation strategies, but they made no difference.

With only 8 Aurora transceivers, the FPGA is roughly 25% utilized. About 60% of SLR1 is occupied, SLR0 is about 20% utilized, SLR2 has a little logic in it, and SLR3 is empty.

Is there a way to determine what is causing this over-constrained error? Is there a better way to encourage Vivado to place logic more uniformly in the device.

Thanks,

Tom

 

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2 Replies
roym
Moderator
Moderator
484 Views
Registered: ‎07-30-2007

When I look at the Aurora wizard it requires that you place the GT's.  If you have done that then there is no need to constrain them as you have.  If you are trying to move the GT's from where the aurora wizard placed them then there is a conflict in the placement.  In vivado you can do a "find in files" on GTXE2_CHANNEL and it should show any hidden placement done such as in my example:

set_property LOC GTXE2_CHANNEL_X0Y0 [get_cells aurora_64b66b_0_block_i/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gtx_inst/gtxe2_i]
set_property LOC GTXE2_CHANNEL_X0Y4 [get_cells aurora_64b66b_0_block_i/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gtx_inst_lane1/gtxe2_i]

This would be the proper way to contrain the locations instead of doing each pin and it appears aurora demands you do this in the wizard.




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eschidl
Xilinx Employee
Xilinx Employee
483 Views
Registered: ‎10-19-2011

Hi @tpdrjkt ,

do you get the error message only for one GTX or several?

Did you create a specific IP core for each location? The IP should have the location of the GTX already set inside. Is the example design for each core placing the GTX correctly?

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