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LukasVik
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Registered: ‎04-24-2020

Preamble and SFD in XGMII stream to/from 10G/25G Ethernet PCS/PMA IP

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Hello,

I am using the "1/10/25G Switching Ethernet Subsystem" IP in 32-bit PCS/PMA configuration. From what I gather this IP instantiates the "10G/25G Ethernet Subsystem" IP.

The data interface when in 10G mode is XGMII. From PG292 the interface looks like this, which seems reasonable:

screenshot.png

My qustion regards whether or not preamble and Start Frame Delimiter (SFD) bytes are present in the data stream.

When receiving, after the /S/ byte will there be 0-7 bytes of preamble, and then one SFD byte, and then the data? Or does the PCS/PMS core strip away the preamble and SFD? Conversely when transmitting, shall I send an /S/ byte, a preamble, an SFD byte, and then my data, or does the PCS/PMA core insert preamble and SFD before the packet is transmitted?

I find no mention of preamble/SFD in PG210 or PG292. Apologies if I have missed something.

 

Best regards

Lukas Vik

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nanz
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Registered: ‎08-25-2009

Hi @LukasVik ,

It should be 7 bytes preamble. Which core are you simulating? Is it xxv or switching core? Can you share your xci so I could run the sim too to compare?

Thank you for pointing out the doc issue too. Let me check and I'll let you know if a CR needs to be filed against the doc. 


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nanz
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Registered: ‎08-25-2009

Hi @LukasVik ,

Yes, there will be preamble, and then one SFD byte, and then the data. 

The best way to find the answer is to run the example design simulation. Hope this helps. 

nanz_0-1619089250964.png

 


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Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

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LukasVik
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Registered: ‎04-24-2020

Hello @nanz and thank for the reply.

I did not know of the example design simulation. Thank you for the tip, that will be useful in the future!

Note that my question regarded the 32-bit XGMII interface, while your screenshot shows the 8-bit GMII interface. However, by running the example design simulation of the 10/25G IP I did find that the preamble and SFD octets are indeed included:

ethernet_preamble.png

However I do have a followup question to this. This simulation show the transmission of six preamble octets before the SFD and data. Does the ethernet standard not require seven preamble octets? Is this legal?

 

Best regards

Lukas

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LukasVik
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Registered: ‎04-24-2020

Also, quick side note: There is an error/typo in a figure in PG292:

doc.png

The three byte lanes should be marked with D instead of S.

 

Best regards

Lukas

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nanz
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Registered: ‎08-25-2009

Hi @LukasVik ,

It should be 7 bytes preamble. Which core are you simulating? Is it xxv or switching core? Can you share your xci so I could run the sim too to compare?

Thank you for pointing out the doc issue too. Let me check and I'll let you know if a CR needs to be filed against the doc. 


-------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

-------------------------------------------------------------------------------------------

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LukasVik
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Registered: ‎04-24-2020

Hello again @nanz ,

> It should be 7 bytes preamble.

Okay great, thank you for clarifying!

I was simulating the xxv core. The .xci is attached.

 

Best regards

Lukas

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