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Adventurer
Adventurer
8,436 Views
Registered: ‎09-27-2010

Problem with 10G on VC709. Strange pattern on gt0_rxdata_i.

Hello.

I'm trying to obtain 10G Ethernet on VC709 board.

I'm using Si570 and SI5324 for clocking at 156.25.
I've generated PCS/PMA Core without MDIO and use it with example design code. I try to make Link up using optical loopback, but I have 0100009C (Fault code) on xgmii_rxd and I have following errors on status vector:
PmaPmdRxLinkStatusLatchingLow = 0 LINK DOWN
PmaPmdFault = 0
GlobalPmdRxSignalDetect = 0 ERROR
PcsRxLinkStatusLatchingLow = 0 LINK DOWN
PcsFault; --1 ERROR
PcsRxFaultLatchingHigh = 1 ERROR
PcsRxLocked10GBase_R = 0 ERROR
PcsRxLinkStatus10GBase_R = 0 LINK_DOWN
LatchedLowRxBlockLock = 0 ERROR


In order to figure out what is happening I've connected chipscope to GT0_RXDATA_OUT and GT0_TXDATA_IN of GTH transceiver. On GT0_TXDATA_IN I observe some scrambled data (or so) with correct header "10". But on GT0_RXDATA_OUT I see strange 5555555555555555 pattern with opposite correct "01" header.

If I disconnect GT0_LOOPBACK_IN from PCS/PMA core and make it "010" or "001" (PMA or PCS near end loopback in GTH) I see on GT0_RXDATA_OUT exactly the same that is on GT0_TXDATA_IN ( with delay, of cause). (But PCS/PMA core still shows PcsFault)

I would, probably, think that it's faulty SFPs or something like that, but if I connect my board to 10G switch, It blinks its LED, so it apparently receives my signal and recognizes it.

GTH statuses and controls are following when I receive this strange 5555 ordered set:
gt0_rxuserrdy_i = 1
gt0_rxgearboxslip_i = 0
gt0_gtrxreset_i = 0
gt0_rxpcsreset_i = 0
gt0_rxbufreset_i = 0
gt0_rxbufstatus_i = "000"
gt0_rxresetdone_i = 1
gt0_txuserrdy_i = 1
gt0_qplllock_i = 1

I have no idea what's happening and what does this 55 ordered set means. Any suggestions?

Ilya
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5 Replies
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Adventurer
Adventurer
8,428 Views
Registered: ‎09-27-2010

Re: Problem with 10G on VC709. Strange pattern on gt0_rxdata_i.

yeah, when I make PMA or PCS near end loopback in GTH there is PcsFault on status vector, but I have 7777 (idle) on xgmii_rx
Ilya
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Xilinx Employee
Xilinx Employee
8,414 Views
Registered: ‎02-06-2013

Re: Problem with 10G on VC709. Strange pattern on gt0_rxdata_i.

Hi

 

How is the XGMII interface of the PCS PMA core connected and how is the data being driven?

 

How is the signal detect signal connected and what happens if you give an reset to the core.

 

what is the status of the status vector and the MDIO registers when connected to Switch.

Regards,

Satish

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Adventurer
Adventurer
8,398 Views
Registered: ‎09-27-2010

Re: Problem with 10G on VC709. Strange pattern on gt0_rxdata_i.

Thank you for reply.

When I was answering your questions I found that after reset Link is up for some time, so I'm scrutinise now what's happening after that. I'll report to you when I figure out more.

Ilya
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Adventurer
Adventurer
8,351 Views
Registered: ‎09-27-2010

Re: Problem with 10G on VC709. Strange pattern on gt0_rxdata_i.

>>> How is the XGMII interface of the PCS PMA core connected and how is the data being driven?

XGMII interface is connected to MAC coreand it sends 070707... idle code on xgmii_txd. But some times it substitute 07 by 03 or 06? I don't know what does it mean.

 

>>>How is the signal detect signal connected and what happens if you give an reset to the core.

>>>what is the status of the status vector and the MDIO registers when connected to Switch.

I take signal detect signal from SFP LOS pin (SFPSignalDetect <= not SFP1_LOS_LS;)

I have no MDIO interface in my core but I can show you status_vector and core_status vectors of the core

just after PCSResetDone = 1
core_status = 00000001 (Link UP)
gt0_txdata_i - something like scrambled data
xgmii_txd = 07070707 (sometime 7 becomes 3 or 6)
both headers are "10"
clk156Locked = 1
PmaStatusVec.PmaPmdRxLinkStatusLatchingLow = 1
PcsPmaStatusVec.PmaPmdFault = 0
PcsPmaStatusVec.PmaPmdRxFaultLatchingHigh = 0
PcsPmaStatusVec.PmaPmdTxFaultLatchingHigh = 0
PcsPmaStatusVec.GlobalPmdRxSignalDetect = 1
PcsPmaStatusVec.PcsRxLinkStatusLatchingLow = 0
PcsPmaStatusVec.PcsFault = 1
PcsPmaStatusVec.PcsRxFaultLatchingHigh = 1        Why it can be 1 just after reset?
PcsPmaStatusVec.PcsTxFaultLatchingHigh = 0
PcsPmaStatusVec.PcsRxLocked10GBase_R = 1
PcsPmaStatusVec.PcsHighBer10GBase_R = 0
PcsPmaStatusVec.PcsRxLinkStatus10GBase_R = 1
PcsPmaStatusVec.LatchedHighRxHighBer = 0
PcsPmaStatusVec.LatchedLowRxBlockLock = 0        Why it's 0 even when reset is present?
---------------------
then after 19500 clocks of 156.25Mhz simultaneously
gt0_rxdata_i become 0000

clk156Locked  becomes 0 (mmcme in PcsPmaModule_block has lost lock)
core_status becomes 00000000 (Link down)
PmaStatusVec.PmaPmdRxLinkStatusLatchingLow becomes 0
PmaStatusVec.GlobalPmdRxSignalDetect becomes 0
PcsPmaStatusVec.PcsRxLocked10GBase_R becomes 0
PcsPmaStatusVec.PcsRxLinkStatus10GBase_R becomes 0
PcsPmaResetDone becomes 0
----------------------
then after 5000 clocks
gt0_rxdata_i become 5555...  (?)
PcsPmaResetDone becomes 1

 

Why clk156Locked  can be lost?

Shall I reset MAC core after PcsPmaResetDone = 1?

Ilya
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Adventurer
Adventurer
8,326 Views
Registered: ‎09-27-2010

Re: Problem with 10G on VC709. Strange pattern on gt0_rxdata_i.

Hi! It's me again.

I've found and corrected a few issues with reset sequence and clocks, but problem is still there.

Now it's clear that second reset of RX part of GTH is caused by unpull watchdog logic going of due to persistent 5555 pattern presented on rx_data output of GTH tranceiver. So, that's why I want to ask you what can be a cause of that 5555 pattern on GTH. It's obvious that it's some special pattern, because cable unpull logic in example design is tuned to "0101" or "1010" or "0000" patterns which indicates that cable is unpulled.

Ilya
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