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lcllcl001
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Visitor
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Registered: ‎03-02-2021

QA_PIN_driver_for_RGMII_interface_ofAXI_1G2.5G Ethernet Subsystem

Hi


I am trying to use an AXI 1G/2.5G Ethernet Subsystem controller to switch between 2 Ethernet ports .
The downloaded example design will be compiled successfully.
I made the following changes.

lcllcl001_0-1614739724059.png

After the modification, I encountered the following error when compiling the VIVAO project.

[DRC REQP-58] ibuf_connects_I_active: IBUF inst_zcu102_hpc0_axieth_wrapper/zcu102_hpc0_axieth_i/axi_ethernet_0/inst/mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rgmii_rx_ctl_ibuf_i
pin I has an invalid driver inst_RM_SELE_ETH0/MAC_ENET_RX_DV_INST_0.
[DRC REQP-58] ibuf_connects_I_active: IBUF inst_zcu102_hpc0_axieth_wrapper/zcu102_hpc0_axieth_i/axi_ethernet_0/inst/mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rgmii_rxc_ibuf_i
pin I has an invalid driver inst_RM_SELE_ETH0/MAC_ENET_RX_CLK_INST_0.

Could you tell me how to solve this issue?

For details,please the attachment.

Thanks and Best Regards.

Chunli Liang

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nanz
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Registered: ‎08-25-2009

Hi @lcllcl001 ,

Please check the following thread and see if this helps:

https://forums.xilinx.com/t5/Implementation/DRC-REQP-58-IBUF-P-I-has-an-invalid-driver/m-p/904069#M22805


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lcllcl001
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Registered: ‎03-02-2021

Hi nanz

Thank you for your advice.

But I want to realize the method of the RGMII_interface port switch.

So I think I must add the logic between the RGMII_interface and the pad of FPGA package.

Now I found the RGMII_interface in the zcu102_hpc0_axieth_i_i_6 IP.

lcllcl001_0-1614854400938.png

 

I think it can not be changed,is it right?

I am trying to change the source of bd_717f_mac_0_rgmii_v2_0_if.v.

I comment the source below.

// (* DONT_TOUCH = "yes" *) IBUF rgmii_rx_ctl_ibuf_i (
    // .I              (rgmii_rx_ctl),
   //  .O              (rgmii_rx_ctl_ibuf)
 // );

But it is always error as below.

[DRC REQP-58] ibuf_connects_I_active: IBUF inst_zcu102_hpc0_axieth_wrapper/zcu102_hpc0_axieth_i/axi_ethernet_0/inst/mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rgmii_rx_ctl_ibuf_i pin I has an invalid driver inst_zcu102_hpc0_axieth_wrapper/zcu102_hpc0_axieth_i_i_6
[DRC REQP-58] ibuf_connects_I_active: IBUF inst_zcu102_hpc0_axieth_wrapper/zcu102_hpc0_axieth_i/axi_ethernet_0/inst/mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rgmii_rxc_ibuf_i pin I has an invalid driver inst_zcu102_hpc0_axieth_wrapper/zcu102_hpc0_axieth_i_i_7

Do I have some method to across the error?

Thanks and Best Regards

Chunli Liang

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nanz
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Registered: ‎08-25-2009

Hi @lcllcl001 ,

So there should not be logics added between RGMII pins and pad FAPG. 

The errors seem to still indicate this - rgmii_rx_ctl_ibuf_i is used? Are you sure this has been removed from the design?

In the meantime, I'd suggest running through AXI Ethernet RGMII example design first and do a comparison.


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lcllcl001
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Registered: ‎03-02-2021

Hi nanz

Thank you for your reply.

>>So there should not be logics added between RGMII pins and pad FAPG.

→But I want to realize the function that switch the RGMII I/F to the port(I want to communicate).

   So I want to add switch logic between the RGMII I/F and the connectors.

   Do you mean if I add the  logic between the RGMII I/F and the connectors,

   it must be errors?The IP has the restrict that can not add logic between the rgmii_rx_ctl and the connector.

   In fact,I add two not gate between the rgmii_rx_ctl and the connector.

   It is also errors.

   

lcllcl001_0-1614901166310.png

[Place 30-378] Input pin of input buffer zcu102_hpc0_axieth_i/axi_ethernet_0/inst/mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rgmii_rx_ctl_ibuf_i/IBUFCTRL_INST has an illegal connection to a logic constant value.
[Place 30-378] Input pin of input buffer zcu102_hpc0_axieth_i/axi_ethernet_0/inst/mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rgmii_rx_ctl_ibuf_i/INBUF_INST has an illegal connection to a logic constant value.
[Place 30-99] Placer failed with error: 'IO Clock Placer stopped due to earlier errors. Implementation Feasibility check failed, Please see the previously displayed individual error or warning messages for more details.'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
[Common 17-69] Command failed: Placer could not place all instances

 

>>The errors seem to still indicate this - rgmii_rx_ctl_ibuf_i is used? Are you sure this has been removed from the design?

→I can not confirm that.Because  it has errors.

>>In the meantime, I'd suggest running through AXI Ethernet RGMII example design first and do a comparison.

→Thank you.The example is OK.I can compile it successfully .
 
Thanks and Best Regards.
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nanz
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Moderator
262 Views
Registered: ‎08-25-2009

Hi @lcllcl001 ,

Yes, the tool expects a direct connection between RGMII pins to connector.

For the errors, you can check out this AR:

https://www.xilinx.com/support/answers/60131.html


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If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

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