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Adventurer
Adventurer
2,087 Views
Registered: ‎11-04-2015

Question about 10GBase-R

Hi,

 

when configuring a Kintex 7 transceiver for "10GBASE-R" I choose the following parameters: (see attachment)

Line Rate RX/TX = 10.3125 Gbps

Reference Clock = 156.25 MHz

External Data Width RX/TX = 64 bit

Encoding RX/TX = 64/66

Internal Data Width = 32 bit

DRP System Clock = 156.25 MHz

 

When opening the Example Project (Vivado 2017.2) and simulating it I can see that the USER_CLK of the data generator block

has a period of 6.2ns (that is 6.4 * 64/66), I would have expected 6.4ns (156,25 MHz).

 

Why does the user clock not have 156.25MHz?

 

Thank you.

 

Rgds, Noreeli

 

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2 Replies
Xilinx Employee
Xilinx Employee
2,070 Views
Registered: ‎02-06-2013

Re: Question about 10GBase-R

HI

 

Yes the user clock will be 322.2Mhz and Userclk2 will be at 161.1Mhz to take care of the Pause cycles  of the gearbox used in 64/66 encoding modes.

 

Refer  TXUSRCLK and TXUSRCLK2 Generation and gearbox section of UG476 to get more details on the clocking.

 

 

 

Regards,

Satish

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Adventurer
Adventurer
2,004 Views
Registered: ‎11-04-2015

Re: Question about 10GBase-R

Thank you for your reply.

 

When looking at the example design simulation (see attachment) I can see that the Ready signal coming out of the

transceiver block is deasserted for two user clock cycles (as shown in documentation UG476) but the Ready signal going into the data generator module is deasserted for just one clock cycle. How does that discrepancy arise?

 

Rgds, Noreeli

pause_rdy.GIF
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