07-26-2017 08:00 AM
when configuring a Kintex 7 transceiver for "10GBASE-R" I choose the following parameters: (see attachment)
Line Rate RX/TX = 10.3125 Gbps
Reference Clock = 156.25 MHz
External Data Width RX/TX = 64 bit
Encoding RX/TX = 64/66
Internal Data Width = 32 bit
DRP System Clock = 156.25 MHz
When opening the Example Project (Vivado 2017.2) and simulating it I can see that the USER_CLK of the data generator block
has a period of 6.2ns (that is 6.4 * 64/66), I would have expected 6.4ns (156,25 MHz).
Why does the user clock not have 156.25MHz?
07-26-2017 08:46 AM
Yes the user clock will be 322.2Mhz and Userclk2 will be at 161.1Mhz to take care of the Pause cycles of the gearbox used in 64/66 encoding modes.
Refer TXUSRCLK and TXUSRCLK2 Generation and gearbox section of UG476 to get more details on the clocking.
07-27-2017 07:54 AM
Thank you for your reply.
When looking at the example design simulation (see attachment) I can see that the Ready signal coming out of the
transceiver block is deasserted for two user clock cycles (as shown in documentation UG476) but the Ready signal going into the data generator module is deasserted for just one clock cycle. How does that discrepancy arise?