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az23
Contributor
Contributor
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Registered: ‎05-31-2018

Question regarding PHY used for 1G/2.5G Ethernet PCS/PMA for 1000 Base X config

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I was wondering if you could give any additional info regarding the 1000 Base X configuration for the 1G/2.5G Ethernet PCS/PMA IP Block, specifically regarding the PHY that it uses. We have it connected through to GEM0 on the zcu111, following something similar to the reference provided in the xapp1305 diagram, see Figure 1 https://www.xilinx.com/support/documentation/application_notes/xapp1305-ps-pl-based-ethernet-solution.pdf.

The confusion stems that although our design does not seem to use the TI DP83867IRPAP Ethernet RGMII PHY, and in fact we have explicitly disabled gem3 just in case for that, we are still able to read and write to phy registers akin to the ones on the TI PHY chip. They correspond to the bits here (see https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/145031176/Reading+PHY+registers+over+MDIO+via+the+PHY+Management+GEM+Register), and are accessible through u-boot when we do an mii dump, as well as through some custom u-boot and kernel driver modifications we’ve done:

RFSoC > mii dump 0 0
0. (0140) -- PHY control register --
(8000:0000) 0.15 = 0 reset
(4000:0000) 0.14 = 0 loopback
(2040:0040) 0. 6,13 = b10 speed selection = 1000 Mbps
(1000:0000) 0.12 = 0 A/N enable
(0800:0000) 0.11 = 0 power-down
(0400:0000) 0.10 = 0 isolate
(0200:0000) 0. 9 = 0 restart A/N
(0100:0100) 0. 8 = 1 duplex = full
(0080:0000) 0. 7 = 0 collision test enable
(003f:0000) 0. 5- 0 = 0 (reserved)


RFSoC > mii dump 0 1
1. (01c4) -- PHY status register --
(8000:0000) 1.15 = 0 100BASE-T4 able
(4000:0000) 1.14 = 0 100BASE-X full duplex able
(2000:0000) 1.13 = 0 100BASE-X half duplex able
(1000:0000) 1.12 = 0 10 Mbps full duplex able
(0800:0000) 1.11 = 0 10 Mbps half duplex able
(0400:0000) 1.10 = 0 100BASE-T2 full duplex able
(0200:0000) 1. 9 = 0 100BASE-T2 half duplex able
(0100:0100) 1. 8 = 1 extended status
(0080:0080) 1. 7 = 1 (reserved)
(0040:0040) 1. 6 = 1 MF preamble suppression
(0020:0000) 1. 5 = 0 A/N complete
(0010:0000) 1. 4 = 0 remote fault
(0008:0000) 1. 3 = 0 A/N able
(0004:0004) 1. 2 = 1 link status
(0002:0000) 1. 1 = 0 jabber detect
(0001:0000) 1. 0 = 0 extended capabilities

So, my question is, what PHY is the 1G/2.5G Ethernet PCS/PMA IP Block actually using, and where can we get more information about its register contents? We were looking through the register set for the gem module here https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html, but they don’t seem to have anything regarding the PHY or its register contents.

In Vivado, when configuring the IP Block, there is a Device Specific Transciever or LVDS Serial option to select for Physical Interface, and we have selected Device Specific Transceiver by default. Is there any more information perhaps for the Device Specific Transciever register set we can find, or is this the wrong path to take?

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claytonr
Xilinx Employee
Xilinx Employee
856 Views
Registered: ‎08-15-2018

Hi @az23,

To follow up on @nanz's answer, I'd like to add that the PCS/PMA IP itself acts like an internal PHY, and those MDIO registers you are reading are from the PCS/PMA IP.

 

The MDIO reference is available here in the PCS/PMA PG047:

https://www.xilinx.com/support/documentation/ip_documentation/gig_ethernet_pcs_pma/v16_1/pg047-gig-eth-pcs-pma.pdf

(Starts at the bottom of page 46)

 

To prove this to yourself, you can use the MII tool again, but instead do:

mii info

Which will query the MDIO bus for every PHY address (0-31) and dump all responses that come back. You should see the address that the PCS/PMA IP has been assigned via the phyaddr signal in your Vivado design show up in that list.

 

Hope this helps!

 

Thanks,

Clayton

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nanz
Moderator
Moderator
869 Views
Registered: ‎08-25-2009

Hi @az23 ,

The PHY register information should be referred to the PHY datasheet. Xilinx has only used/tested some standard PHYs as per our evalation board. (the PHY info can be found in each evalation board's guide)

The IP itself should be able to interface the supported standards' PHYs in general (SGMII PHY or 1000BASE-X).

We also have transceiver User Guides which you can refer to for each GT types. Try to find which transcer you are using specifically on the board and then take a look at the User Guide. 

 


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claytonr
Xilinx Employee
Xilinx Employee
857 Views
Registered: ‎08-15-2018

Hi @az23,

To follow up on @nanz's answer, I'd like to add that the PCS/PMA IP itself acts like an internal PHY, and those MDIO registers you are reading are from the PCS/PMA IP.

 

The MDIO reference is available here in the PCS/PMA PG047:

https://www.xilinx.com/support/documentation/ip_documentation/gig_ethernet_pcs_pma/v16_1/pg047-gig-eth-pcs-pma.pdf

(Starts at the bottom of page 46)

 

To prove this to yourself, you can use the MII tool again, but instead do:

mii info

Which will query the MDIO bus for every PHY address (0-31) and dump all responses that come back. You should see the address that the PCS/PMA IP has been assigned via the phyaddr signal in your Vivado design show up in that list.

 

Hope this helps!

 

Thanks,

Clayton

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az23
Contributor
Contributor
829 Views
Registered: ‎05-31-2018

Thank you guys, I believe that answers it!

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