We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Visitor lior.mor
Registered: ‎09-03-2017

Questions about CPRI LogiCore v8.7 with ZYNC Ultrascale+ zu19e1924, Clocking and more


We are designing a project with ZYNC Ultrascale+, zu19e1924, using also the CPRI LogiCore in the project.


I have a few questions which I’ll be happy to discuss about, especially about the clocking and the abilities to change them on the fly.
Also, about the Transceivers (We want to be set to 24G, 12G etc.).


Our design intends to use 36 units of CPRI LogiCore in this project.


Do I need to consider an MMCM unit for each CPRI unit in this project?
May I use a single MMCM for 7 units? I saw in the data sheets that a single MMCM unit can split 7 clocks. But, how can it be changed? Can it be configured on the fly? Or just once before synthesis?.

In the pg056-cpri_v87.pdf, p.161 it's written that in Ultrascale+ devices, there is no use of MMCM in the clocking. So, who pushes the clock? If I need to change the input clock, to produce it in other rates, how can it be done?

From where do I need to support the clk_in to the transceiver \ CPRI LogiCore?


Also, about the support layer - which can be instantiated in the CPRI LogiCore settings - How can I connect and share the support layer for multiple CPRI LogiCores? In continue to the former questions, if the CPRI LogiCores unit use different clocks (rates), how can it be done?


Thank you very much in advance,


0 Kudos
1 Reply
Xilinx Employee
Xilinx Employee
Registered: ‎05-01-2013

Re: Questions about CPRI LogiCore v8.7 with ZYNC Ultrascale+ zu19e1924, Clocking and more

Could you create an IP core example design first? Besides IP core itself, the example design also provides the necessary clocking and resets logic source codes. You can understand the design hierarchical easily.

As you can see, with the different settings, sometimes MMCM may be not needed if the clock frequency is already the correct one. The core can use the clock (e.g GT output) directly via BUFG or BUFR.

If MMCM is needed, I don't suggest you share RX clocking. As RX clock is recovered from the link partner, every lane may has its own RX RECCLK.

TX clock can be shared, however all the CPRI have to run in the same speed. Or it means that all CPRI should work by following the CPRI whose clock is shared by the others.


0 Kudos