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Registered: ‎10-19-2016

RFSOC/MPSOC Ethernet generic reset with GPIO in Device tree

Hi all,

in my company we have developed a custom board based on RFSoc.

In our design, the reset of the Gigabit Ethernet MDIO is done using a MIO of the PS.

The purpose is to be able to use the GbE interface in u-boot and Linux.

To do so, I understood I have to configure the reset pin in the device tree.

I have found few examples on Xilinx forums and on Internet, but despite all my tries, I was unable to make the GbE interface detected automatically by u-boot.

When I toggle the GPIO with XSCT before actually run u-boot, then the GbE interface is correctly detected. But, if I load and run u-boot, then the GbE is not detected.

Here is the XSCT script I use to configure the board:



targets -set -filter {name =~ "PSU"}
mwr 0xffca0038 0x1ff
after 500
targets -set -filter {name =~ "MicroBlaze PMU"}
dow {E:\tmp\images\linux\pmufw.elf}
after 500
targets -set -filter {name =~ "Cortex-A53 #0"}
rst -processor
dow {E:\tmp\images\linux\executable.elf}
after 3000
dow {E:\tmp\images\linux\bl31.elf}
after 3000
dow {E:\tmp\images\linux\u-boot.elf}



I could configure the GPIO manually using the XSCT commands:



mrd 0xFF0A0244
mwr 0xFF0A0244 0x2
mrd 0xFF0A0248
mwr 0xFF0A0248 0Xb
mrd 0xFF0A0008
mwr 0xFF0A0008  0xFFFD0002



When I do not configure the GPIO with XSCT commands, I have the following output in my console:



Xilinx Zynq MP First Stage Boot Loader
Release 2019.2   Dec 15 2020  -  14:07:04
NOTICE:  ATF running on XCZU25DR/silicon v4/RTL5.1 at 0xfffea000
NOTICE:  BL31: v2.2(release):xilinx_rebase_v2.2_2020.2
NOTICE:  BL31: Built : 11:07:33, Jan  6 2021

U-Boot 2020.01 (Jan 12 2021 - 10:52:42 +0000)

Board: Xilinx ZynqMP
DRAM:  4 GiB
usb dr_mode not found
PMUFW:  v1.1
EL Level:       EL2
Chip ID:        zu25dr
NAND:  0 MiB
In:    serial@ff000000
Out:   serial@ff000000
Err:   serial@ff000000
Bootmode: JTAG_MODE
Reset reason:   EXTERNAL
Configuration GEM Reset
ZYNQ GEM: ff0c0000, mdio bus ff0c0000, phyaddr -1, interface rgmii-id
Could not get PHY for eth0: addr -1

ZYNQ GEM: ff0d0000, mdio bus ff0d0000, phyaddr -1, interface sgmii
Could not get PHY for eth1: addr -1

ZYNQ GEM: ff0e0000, mdio bus ff0e0000, phyaddr -1, interface sgmii
Could not get PHY for eth2: addr -1
No ethernet found.




Here is the IOs connected to the PS:

Custom board with RFSoc, based on ZCU111
Banks 500-501-502 configuration
QSPI FLASH on dual bus : MIO0-MOI5 and MIO7-MIO12
UART console : MIO14-MIO15
UART internal : MIO17-MIO17
I2C master : MIO18-MIO19
GPIO internal to board : MIO20
GPIO internal to board : MIO21
PCI-express reset : MIO26
GPIO Gigabit reset : MIO27
GPIO Gigabit interrupt : MIO28
GPIO USB reset : MIO29
GPIO internal to board : MIO30
GPIO internal to board : MIO31

Gigabit MDIO (Gem1) : MIO38-MIO51

all other IO of these banks are not connnected
Bank 505 GT usage:
PCI-express for NVME drive : Bank505, 2 lanes GT0 and GT1
Ethernet Gigabit 1000base-T: Bank505, GT2 and GT3

QSPI Flash modules : MT25QU02GCBB8E12
GbE MDIO : Marvell 88E1512
USB2.0 ULPI : Microchip USB3320

I attached the device tree I use.

Any help will be welcome!!!




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