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Adventurer
Adventurer
3,297 Views
Registered: ‎06-23-2016

RapidIO software

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Hi,

 

I've been using the IP srio gen2, works well, I am able to send and receive data using axi stream I/O logical port of the IP. The think is I have to create myself packets in HELLO format to send transactions like NWRITE or NREAD for example. I wonder if there is a way of using software functions to issue such transactions and response ?

 

 

Thanks

K@ppa

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Xilinx Employee
Xilinx Employee
2,835 Views
Registered: ‎02-06-2013

Re: RapidIO software

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Hi

 

Yes the core is transparent.

 

You can find more details on the packet format and input/output handling from below doc

 

http://www.xilinx.com/support/documentation/ip_documentation/srio_gen2/v4_0/pg007_srio_gen2.pdf

Regards,

Satish

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Adventurer
Adventurer
3,243 Views
Registered: ‎06-23-2016

Re: RapidIO software

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UP

Is it possible to put linux on a microblaze, and then use linux srio drivers?

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Xilinx Employee
Xilinx Employee
3,225 Views
Registered: ‎02-06-2013

Re: RapidIO software

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Hi

 

The core comes with an example design using which you can generate various packets,refer PG007.

 

There are no Linux drivers available with the core, you need develop and it is possible to transmit packets from the application level too.

Regards,

Satish

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Adventurer
Adventurer
2,885 Views
Registered: ‎06-23-2016

Re: RapidIO software

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Does that mean that the IP is "transparent" to the transactions it receives and sends?

I mean, for example, if it receives a NWRITE to a certain address and data, it would do nothing except checking the conformity to the rapidio specs and if so, will write it to the axis_iorx channel?

One should then write a software layer to decode the transaction and do the WRITE with a CPU for example ? 

What about the transaction that require a data for Response? Has the IP any track of it?

 

Thanks

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Xilinx Employee
Xilinx Employee
2,836 Views
Registered: ‎02-06-2013

Re: RapidIO software

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Hi

 

Yes the core is transparent.

 

You can find more details on the packet format and input/output handling from below doc

 

http://www.xilinx.com/support/documentation/ip_documentation/srio_gen2/v4_0/pg007_srio_gen2.pdf

Regards,

Satish

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