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Explorer
Explorer
354 Views
Registered: ‎10-27-2013

Read and write access to AXI lite of AXI ethernet Lite

Hi,

 Can I initiate read and write access simultaneouly to AXI Ethernet Lite core??

when read AXI cycles to IP are running can I also initiate write cycles?? Will the core respond.

 

Please suggest

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-01-2013

回复: Read and write access to AXI lite of AXI ethernet Lite

No, I don't think AXI lite can do it.

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Explorer
Explorer
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Registered: ‎10-27-2013

回复: Read and write access to AXI lite of AXI ethernet Lite

As of now I do not have data to elaborate. I will update my findings.

I tried to do read and write access simultaneouly, where in my tentative observation is

""Write cycle got extented and Read was responded with a valid followed by completion of write cycle""

I will post the result once confirmed.

This query was for AXI Ethernet lite IP core. In this case there is only one Axi Lite bus to communicate with IP. So data receive and transmit is not possible simulatneously. I will have to wait for data reading from receive buffer to complete before triggering data write to Transmit buffer and vice versa.

So it would be better if I could write to trasmit buffer and read form receive buffer simulatneouly as these are totally independent operations.

I dont know about the internal function of IP core so not sure about support for such an operation. Since I am using VHDL to control Axi ethernet lite core I do not need to have wait cycles.

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Explorer
Explorer
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Registered: ‎10-27-2013

回复: Read and write access to AXI lite of AXI ethernet Lite

AXi Lite simultneous read write for AXI Ethernet  Lite IP.

I am able to set MACID suing simultanious read write access

Read/write cycles are generated simulataneouly. READ is preset to addr 0x07fc

Please let me know opinion

Xilinx_Axi.jpg
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Adventurer
Adventurer
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Registered: ‎03-21-2016

回复: Read and write access to AXI lite of AXI ethernet Lite

Hey. I don’t understand why reading and writing at the same time. The diagram shows that reading is first performed, then recording. In my opinion, the interface does not support simultaneous reading and writing (should be in the specification http://www.gstitt.ece.ufl.edu/courses/fall15/eel4720_5721/labs/refs/AXI4_specification.pdf).

When I wrote the master for AxiEthernet, I had no task of reading and writing at the same time.

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